remove pwr_reset

apple-one.qsf

@@ -175,7 +175,6 @@ set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
 set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
 set_global_assignment -name VERILOG_FILE rtl/apple1.v
 set_global_assignment -name VERILOG_FILE rtl/clock.v
-set_global_assignment -name VERILOG_FILE rtl/pwr_reset.v
 set_global_assignment -name VERILOG_FILE rtl/ram.v
 set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
 set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v

rtl/apple1.v

@@ -24,7 +24,7 @@
 
 module apple1(
     input  clk7,                // 7 MHz master clock
-    input  rst_n,               // active low synchronous reset (needed for simulation)
+    input  reset,               // reset
 	 
 	 input  cpu_clken,           // cpu clock enable
 
@@ -61,28 +61,13 @@ assign ram_wr   = we & ram_cs;
     wire [7:0] cpu_dout;
     wire we;
 
-    //////////////////////////////////////////////////////////////////////////
-    // Clocks
-
-
-    //////////////////////////////////////////////////////////////////////////
-    // Reset
-
-    wire rst;
-    pwr_reset pwr_reset(
-        .clk7(clk7),
-        .rst_n(rst_n),
-        .enable(cpu_clken),
-        .rst(rst)
-    );
-
     //////////////////////////////////////////////////////////////////////////
     // 6502
 
     arlet_6502 arlet_6502(
         .clk    (clk7),
         .enable (cpu_clken),
-        .rst    (rst),
+        .rst    (reset),
         .ab     (addr),
         .dbi    (cpu_din),
         .dbo    (cpu_dout),
@@ -108,7 +93,7 @@ assign ram_wr   = we & ram_cs;
     wire [7:0] ps2_dout;
     ps2keyboard keyboard(
         .clk7(clk7),
-        .rst(rst),
+        .rst(reset),
         .key_clk(ps2_clk),
         .key_din(ps2_din),
         .cs(keyboard_cs),
@@ -119,7 +104,7 @@ assign ram_wr   = we & ram_cs;
     display display(
         .clk(clk7),
         .enable(display_cs & cpu_clken),
-        .rst(rst),
+        .rst(reset),
 
         .vga_h_sync(vga_h_sync),
         .vga_v_sync(vga_v_sync),

rtl/apple1_mist.sv

@@ -258,7 +258,7 @@ wire [7:0] bus_dout = basic_cs ? basic_dout :
 apple1 apple1 
 (
 	.clk7(clk7),
-	.rst_n(~reset_button),
+	.reset(reset_button),
 	
 	.cpu_clken(cpu_clken),     // apple1 outputs the CPU clock enable
 	
@@ -421,7 +421,7 @@ wire cpu_clken;  // provides the cpu clock enable signal derived from main clock
 //wire cpu_clken;
 clock clock(
   .clk7     ( clk7          ),   // input: main clock
-  .rst_n    ( ~reset_button ),   // input: reset signal
+  .reset    ( reset_button  ),   // input: reset signal
   .cpu_clken( cpu_clken     )    // output: cpu clock enable
 );
 

rtl/clock.v

@@ -26,7 +26,7 @@
 module clock
 (
     input clk7,             // 7MHz clock master clock
-    input rst_n,            // active low synchronous reset
+    input reset,            // reset
 
     // Clock enables
     output reg cpu_clken    // 1MHz clock enable for the CPU and devices
@@ -44,7 +44,7 @@ module clock
 	  reg [4:0] clk_div;
 	  always @(posedge clk7)
 	  begin
-			if ((clk_div == 7) || (rst_n == 1'b0))
+			if (clk_div == 7 || reset )
 				 clk_div <= 0;
 			else
 				 clk_div <= clk_div + 1'b1;