Apple-1-HW/Apple1_MiST
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do not use system reset for display

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This commit is contained in:
nino-porcino 2022-05-07 11:39:28 +02:00
parent 6c292189f9
commit a41bb35646
2 changed files with 5 additions and 3 deletions
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5
rtl/apple1.v
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@ -24,6 +24,7 @@
module apple1(
input reset, // reset
input fpga_reset, // fpga reset for one-time reset of display and keyboard
input sys_clock, // system clock
input pixel_clken, // 7 MHz pixel clock
@ -125,7 +126,7 @@ module apple1(
wire cls_key;
ps2keyboard keyboard(
.clk(sys_clock),
.rst(reset),
.rst(fpga_reset),
.key_clk(ps2_clk),
.key_din(ps2_din),
.cs(keyboard_cs),
@ -138,7 +139,7 @@ module apple1(
wire PB7; // (negated) display ready (PB7 of CIA)
display display(
.reset(reset),
.reset(fpga_reset),
.sys_clock(sys_clock),
.pixel_clken(pixel_clken),

3
rtl/apple1_mist.sv
View File

@ -350,6 +350,7 @@ end
apple1 apple1
(
.reset(reset_button),
.fpga_reset(fpga_reset),
.sys_clock ( sys_clock ), // system clock
.cpu_clken ( cpu_clken & ~is_downloading ), // CPU clock enable
@ -585,7 +586,7 @@ wire cpu_clock; // cpu clock for the sdram controller sync
clock clock(
.sys_clock ( sys_clock ), // input: main clock
.reset ( reset_button ), // input: reset signal
.reset ( fpga_reset ), // input: reset signal
.cpu_clock ( cpu_clock ),
.cpu_clken ( cpu_clken ), // output: cpu clock enable (phi2)