rename sdram_* into bus_*; use assign instead of always block; optional SDRAM at $4000
This commit is contained in:
nino-porcino
parent
5dfe5a041c
commit
aa6042cabd
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@ -81,6 +81,7 @@ localparam CONF_STR = {
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"O2,TMS9918 output,Off,On;",
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`endif
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"O3,Audio monitor,tape in,tape out;",
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"O4,SDRAM at $4000,off,on;",
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"T6,Reset;",
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"V,",`BUILD_DATE
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`ifdef USE_SID
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@ -91,6 +92,12 @@ localparam CONF_STR = {
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`endif
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};
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`ifdef USE_TMS
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localparam BLOCKRAM_SIZE = 'hA000;
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`else
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localparam BLOCKRAM_SIZE = 'hC000;
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`endif
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localparam conf_str_len = $size(CONF_STR)>>3;
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wire st_reset_switch = buttons[1];
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@ -102,6 +109,7 @@ wire [1:0] switches;
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wire st_tms9918_output = status[2];
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wire st_audio_mon_tape_in = ~status[3];
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wire st_menu_reset = status[6];
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wire st_sdram_expansion = status[4];
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wire scandoubler_disable;
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wire ypbpr;
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@ -123,7 +131,13 @@ wire fpga_reset = ~pll_locked;
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wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
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wire osd_clock; // cpu x 7 x 2 for the OSD menu
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//wire F7M_clock; // cpu x 7 (SDRAM/8) for downloader
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`ifdef USE_TMS
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wire vdp_clock; // tms9918 x 2 for osd menu
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`endif
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assign SDRAM_CLK = sys_clock;
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pll pll
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(
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@ -131,9 +145,12 @@ pll pll
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.locked(pll_locked),
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.c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
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//.c1( F7M_clock ), // cpu x 7 (SDRAM/8) for downloader
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.c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
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.c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
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// .c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
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`ifdef USE_TMS
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.c4( vdp_clock ) // tms9918 x 2 for osd menu (10.738635 x 2 = 21.47727)
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`endif
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);
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/******************************************************************************************/
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@ -186,12 +203,12 @@ downloader
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wire [7:0] ram_dout;
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// low system RAM
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ram #(.SIZE(16384)) ram(
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// low system RAM
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ram #(.SIZE(BLOCKRAM_SIZE)) ram(
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.clk (sys_clock ),
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.address(sdram_addr[15:0]),
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.w_en (sdram_wr & ram_cs),
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.din (sdram_din ),
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.address(bus_addr[15:0]),
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.w_en (bus_wr & ram_cs),
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.din (bus_din ),
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.dout (ram_dout )
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);
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@ -208,9 +225,9 @@ rom_wozmon rom_wozmon(
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wire [7:0] basic_dout;
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ram #(.SIZE(4096)) rom_basic(
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.clk(sys_clock),
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.address({4'b000, sdram_addr[11:0]}),
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.w_en (sdram_wr & basic_cs),
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.din (sdram_din ),
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.address({4'b000, bus_addr[11:0]}),
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.w_en (bus_wr & basic_cs),
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.din (bus_din ),
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.dout (basic_dout)
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);
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@ -225,7 +242,7 @@ wire CASOUT;
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ACI ACI(
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.clk(sys_clock),
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.cpu_clken(cpu_clken),
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.addr(sdram_addr[15:0]),
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.addr(bus_addr[15:0]),
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.dout(aci_dout),
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.tape_in(CASIN),
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.tape_out(CASOUT)
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@ -266,51 +283,31 @@ end
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @apple1 ****************************************/
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/***************************************** @bus *******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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// SDRAM control signals
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// bus control signals
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wire [24:0] sdram_addr;
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wire [7:0] sdram_din;
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wire sdram_wr;
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wire sdram_rd;
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wire [7:0] sdram_dout;
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wire [24:0] bus_addr;
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wire [7:0] bus_din;
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wire bus_wr;
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wire bus_rd;
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always @(posedge sys_clock) begin
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if(is_downloading && download_wr) begin
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sdram_addr <= download_addr;
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sdram_din <= download_data;
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sdram_wr <= download_wr;
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sdram_rd <= 1'b1;
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end
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else begin
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sdram_addr <= { 9'b0, cpu_addr[15:0] };
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sdram_din <= cpu_dout;
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sdram_wr <= cpu_wr;
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sdram_rd <= 1'b1;
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end
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end
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assign bus_addr = (is_downloading && download_wr) ? download_addr : { 9'b0, cpu_addr[15:0] };
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assign bus_din = (is_downloading && download_wr) ? download_data : cpu_dout;
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assign bus_wr = (is_downloading && download_wr) ? download_wr : cpu_wr;
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assign bus_rd = (is_downloading && download_wr) ? 1'b1 : 1'b1; // TODO provare !wr ??
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wire dummy = is_downloading && download_wr;
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assign LED = ~dummy;
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// ram interface
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wire [15:0] cpu_addr;
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wire [7:0] cpu_dout;
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wire cpu_rd;
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wire cpu_wr;
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wire ram_cs = sdram_addr < 'h4000; // 0x0000 -> 0x3FFF
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wire sdram_cs = sdram_addr >= 'h4000 && sdram_addr <= 'hBFFF; // 0x4000 -> 0xBFFF
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wire aci_cs = sdram_addr >= 'hC000 && sdram_addr <= 'hC1FF; // 0xC000 -> 0xC1FF
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wire basic_cs = sdram_addr >= 'hE000 && sdram_addr <= 'hEFFF; // 0xE000 -> 0xEFFF
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wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFFF
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wire ram_cs = bus_addr <= st_sdram_expansion ? 'h3FFF : 'hBFFF ;
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wire sdram_cs = st_sdram_expansion ? bus_addr >= 'h4000 && bus_addr <= 'hBFFF : 0;
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wire aci_cs = bus_addr >= 'hC000 && bus_addr <= 'hC1FF;
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wire basic_cs = bus_addr >= 'hE000 && bus_addr <= 'hEFFF;
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wire rom_cs = bus_addr >= 'hFF00;
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// experimental SID 6561
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`ifdef USE_SID
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wire sid_cs = sdram_addr >= 'hC800 && sdram_addr <= 'hC8FF; // 0xC800 -> 0xC8FF
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wire sid_cs = bus_addr >= 'hC800 && bus_addr <= 'hC8FF; // 0xC800 -> 0xC8FF
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`else
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wire sid_cs = 0;
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wire sid_dout = 0;
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@ -318,7 +315,7 @@ wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFF
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// experimental TMS9918
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`ifdef USE_TMS
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wire tms_cs = sdram_addr >= 'hCC00 && sdram_addr <= 'hCC01; // 0xCC00 -> 0xCC01
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wire tms_cs = bus_addr >= 'hCC00 && bus_addr <= 'hCC01; // 0xCC00 -> 0xCC01
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`else
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wire tms_cs = 0;
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wire vdp_dout = 0;
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@ -332,6 +329,12 @@ wire [7:0] bus_dout = rom_cs ? rom_dout :
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sdram_cs ? sdram_dout :
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ram_cs ? ram_dout :
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8'b0;
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @apple1 ****************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire reset_key;
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wire poweroff_key;
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@ -348,7 +351,12 @@ reg reset_key_old = 0;
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always @(posedge sys_clock) begin
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reset_key_old <= reset_key;
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end
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wire [15:0] cpu_addr;
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wire [7:0] cpu_dout;
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wire cpu_rd;
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wire cpu_wr;
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apple1 apple1
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(
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.reset(reset_button),
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@ -547,6 +555,8 @@ user_io (
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/***************************************** @sdram *****************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire [7:0] sdram_dout;
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// SDRAM control signals
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assign SDRAM_CKE = 1'b1;
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@ -568,11 +578,11 @@ sdram sdram (
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.init ( !pll_locked ),
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// cpu interface
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.din ( sdram_din ),
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.addr ( sdram_addr ),
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.we ( sdram_wr ),
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.oe ( sdram_rd ),
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.dout ( sdram_dout )
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.din ( bus_din ),
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.addr ( bus_addr ),
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.we ( bus_wr ),
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.oe ( bus_rd ),
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.dout ( sdram_dout )
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);
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/******************************************************************************************/
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@ -596,6 +606,17 @@ clock clock(
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.pixel_clken ( pixel_clken ) // output: pixel clock enable
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);
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @led *******************************************/
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/******************************************************************************************/
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/******************************************************************************************/
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wire dummy = is_downloading && download_wr;
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assign LED = ~dummy;
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/******************************************************************************************/
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/******************************************************************************************/
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/***************************************** @vdp *******************************************/
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@ -626,8 +647,8 @@ always @(posedge vdp_clock) begin
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vdp_ena <= ~vdp_ena;
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end
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wire csr = tms_cs & sdram_rd;
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wire csw = tms_cs & sdram_wr;
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wire csr = tms_cs & bus_rd;
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wire csw = tms_cs & bus_wr;
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wire tms_HS;
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wire tms_VS;
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@ -655,11 +676,11 @@ tms9918
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// control signals
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.csr_n ( ~csr ),
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.csw_n ( ~csw ),
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.mode ( sdram_addr[0] ),
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.mode ( bus_addr[0] ),
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.int_n ( VDP_INT_n ),
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// cpu I/O
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.cd_i ( sdram_din ),
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.cd_i ( bus_din ),
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.cd_o ( vdp_dout ),
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// vram
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@ -694,9 +715,9 @@ sid_top sid_top
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.clock(sys_clock),
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.reset(reset_button),
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.addr(sdram_addr[7:0]),
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.addr(bus_addr[7:0]),
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.wren(cpu_wr & sid_cs),
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.wdata(sdram_din),
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.wdata(bus_din),
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.rdata(sid_dout),
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.potx(0),
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