Apple-1-HW
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Apple1_MiST
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rename sdram_* into bus_*; use assign instead of always block; optional SDRAM at $4000

This commit is contained in:
nino-porcino 2022-05-21 12:48:14 +02:00
parent 5dfe5a041c
commit aa6042cabd
1 changed files with 80 additions and 59 deletions
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139
rtl/apple1_mist.sv
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@ -81,6 +81,7 @@ localparam CONF_STR = {
"O2,TMS9918 output,Off,On;", "O2,TMS9918 output,Off,On;",
`endif `endif
"O3,Audio monitor,tape in,tape out;", "O3,Audio monitor,tape in,tape out;",
"O4,SDRAM at $4000,off,on;",
"T6,Reset;", "T6,Reset;",
"V,",`BUILD_DATE "V,",`BUILD_DATE
`ifdef USE_SID `ifdef USE_SID
@ -91,6 +92,12 @@ localparam CONF_STR = {
`endif `endif
}; };
`ifdef USE_TMS
localparam BLOCKRAM_SIZE = 'hA000;
`else
localparam BLOCKRAM_SIZE = 'hC000;
`endif
localparam conf_str_len = $size(CONF_STR)>>3; localparam conf_str_len = $size(CONF_STR)>>3;
wire st_reset_switch = buttons[1]; wire st_reset_switch = buttons[1];
@ -102,6 +109,7 @@ wire [1:0] switches;
wire st_tms9918_output = status[2]; wire st_tms9918_output = status[2];
wire st_audio_mon_tape_in = ~status[3]; wire st_audio_mon_tape_in = ~status[3];
wire st_menu_reset = status[6]; wire st_menu_reset = status[6];
wire st_sdram_expansion = status[4];
wire scandoubler_disable; wire scandoubler_disable;
wire ypbpr; wire ypbpr;
@ -123,7 +131,13 @@ wire fpga_reset = ~pll_locked;
wire sys_clock; // cpu x 7 x 8 system clock (sdram.v) wire sys_clock; // cpu x 7 x 8 system clock (sdram.v)
wire osd_clock; // cpu x 7 x 2 for the OSD menu wire osd_clock; // cpu x 7 x 2 for the OSD menu
//wire F7M_clock; // cpu x 7 (SDRAM/8) for downloader
`ifdef USE_TMS
wire vdp_clock; // tms9918 x 2 for osd menu wire vdp_clock; // tms9918 x 2 for osd menu
`endif
assign SDRAM_CLK = sys_clock;
pll pll pll pll
( (
@ -131,9 +145,12 @@ pll pll
.locked(pll_locked), .locked(pll_locked),
.c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu .c0( osd_clock ), // cpu x 7 x 2 video clock for OSD menu
//.c1( F7M_clock ), // cpu x 7 (SDRAM/8) for downloader
.c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v) .c2( sys_clock ), // cpu x 7 x 8 system clock (sdram.v)
.c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns // .c3( SDRAM_CLK ), // cpu x 7 x 8 phase shifted -2.5 ns
`ifdef USE_TMS
.c4( vdp_clock ) // tms9918 x 2 for osd menu (10.738635 x 2 = 21.47727) .c4( vdp_clock ) // tms9918 x 2 for osd menu (10.738635 x 2 = 21.47727)
`endif
); );
/******************************************************************************************/ /******************************************************************************************/
@ -186,12 +203,12 @@ downloader
wire [7:0] ram_dout; wire [7:0] ram_dout;
// low system RAM // low system RAM
ram #(.SIZE(16384)) ram( ram #(.SIZE(BLOCKRAM_SIZE)) ram(
.clk (sys_clock ), .clk (sys_clock ),
.address(sdram_addr[15:0]), .address(bus_addr[15:0]),
.w_en (sdram_wr & ram_cs), .w_en (bus_wr & ram_cs),
.din (sdram_din ), .din (bus_din ),
.dout (ram_dout ) .dout (ram_dout )
); );
@ -208,9 +225,9 @@ rom_wozmon rom_wozmon(
wire [7:0] basic_dout; wire [7:0] basic_dout;
ram #(.SIZE(4096)) rom_basic( ram #(.SIZE(4096)) rom_basic(
.clk(sys_clock), .clk(sys_clock),
.address({4'b000, sdram_addr[11:0]}), .address({4'b000, bus_addr[11:0]}),
.w_en (sdram_wr & basic_cs), .w_en (bus_wr & basic_cs),
.din (sdram_din ), .din (bus_din ),
.dout (basic_dout) .dout (basic_dout)
); );
@ -225,7 +242,7 @@ wire CASOUT;
ACI ACI( ACI ACI(
.clk(sys_clock), .clk(sys_clock),
.cpu_clken(cpu_clken), .cpu_clken(cpu_clken),
.addr(sdram_addr[15:0]), .addr(bus_addr[15:0]),
.dout(aci_dout), .dout(aci_dout),
.tape_in(CASIN), .tape_in(CASIN),
.tape_out(CASOUT) .tape_out(CASOUT)
@ -266,51 +283,31 @@ end
/******************************************************************************************/ /******************************************************************************************/
/******************************************************************************************/ /******************************************************************************************/
/***************************************** @apple1 ****************************************/ /***************************************** @bus *******************************************/
/******************************************************************************************/ /******************************************************************************************/
/******************************************************************************************/ /******************************************************************************************/
// SDRAM control signals // bus control signals
wire [24:0] sdram_addr; wire [24:0] bus_addr;
wire [7:0] sdram_din; wire [7:0] bus_din;
wire sdram_wr; wire bus_wr;
wire sdram_rd; wire bus_rd;
wire [7:0] sdram_dout;
always @(posedge sys_clock) begin assign bus_addr = (is_downloading && download_wr) ? download_addr : { 9'b0, cpu_addr[15:0] };
if(is_downloading && download_wr) begin assign bus_din = (is_downloading && download_wr) ? download_data : cpu_dout;
sdram_addr <= download_addr; assign bus_wr = (is_downloading && download_wr) ? download_wr : cpu_wr;
sdram_din <= download_data; assign bus_rd = (is_downloading && download_wr) ? 1'b1 : 1'b1; // TODO provare !wr ??
sdram_wr <= download_wr;
sdram_rd <= 1'b1;
end
else begin
sdram_addr <= { 9'b0, cpu_addr[15:0] };
sdram_din <= cpu_dout;
sdram_wr <= cpu_wr;
sdram_rd <= 1'b1;
end
end
wire dummy = is_downloading && download_wr; wire ram_cs = bus_addr <= st_sdram_expansion ? 'h3FFF : 'hBFFF ;
assign LED = ~dummy; wire sdram_cs = st_sdram_expansion ? bus_addr >= 'h4000 && bus_addr <= 'hBFFF : 0;
wire aci_cs = bus_addr >= 'hC000 && bus_addr <= 'hC1FF;
// ram interface wire basic_cs = bus_addr >= 'hE000 && bus_addr <= 'hEFFF;
wire [15:0] cpu_addr; wire rom_cs = bus_addr >= 'hFF00;
wire [7:0] cpu_dout;
wire cpu_rd;
wire cpu_wr;
wire ram_cs = sdram_addr < 'h4000; // 0x0000 -> 0x3FFF
wire sdram_cs = sdram_addr >= 'h4000 && sdram_addr <= 'hBFFF; // 0x4000 -> 0xBFFF
wire aci_cs = sdram_addr >= 'hC000 && sdram_addr <= 'hC1FF; // 0xC000 -> 0xC1FF
wire basic_cs = sdram_addr >= 'hE000 && sdram_addr <= 'hEFFF; // 0xE000 -> 0xEFFF
wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFFF
// experimental SID 6561 // experimental SID 6561
`ifdef USE_SID `ifdef USE_SID
wire sid_cs = sdram_addr >= 'hC800 && sdram_addr <= 'hC8FF; // 0xC800 -> 0xC8FF wire sid_cs = bus_addr >= 'hC800 && bus_addr <= 'hC8FF; // 0xC800 -> 0xC8FF
`else `else
wire sid_cs = 0; wire sid_cs = 0;
wire sid_dout = 0; wire sid_dout = 0;
@ -318,7 +315,7 @@ wire rom_cs = sdram_addr >= 'hFF00; // 0xFF00 -> 0xFFF
// experimental TMS9918 // experimental TMS9918
`ifdef USE_TMS `ifdef USE_TMS
wire tms_cs = sdram_addr >= 'hCC00 && sdram_addr <= 'hCC01; // 0xCC00 -> 0xCC01 wire tms_cs = bus_addr >= 'hCC00 && bus_addr <= 'hCC01; // 0xCC00 -> 0xCC01
`else `else
wire tms_cs = 0; wire tms_cs = 0;
wire vdp_dout = 0; wire vdp_dout = 0;
@ -332,6 +329,12 @@ wire [7:0] bus_dout = rom_cs ? rom_dout :
sdram_cs ? sdram_dout : sdram_cs ? sdram_dout :
ram_cs ? ram_dout : ram_cs ? ram_dout :
8'b0; 8'b0;
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @apple1 ****************************************/
/******************************************************************************************/
/******************************************************************************************/
wire reset_key; wire reset_key;
wire poweroff_key; wire poweroff_key;
@ -348,7 +351,12 @@ reg reset_key_old = 0;
always @(posedge sys_clock) begin always @(posedge sys_clock) begin
reset_key_old <= reset_key; reset_key_old <= reset_key;
end end
wire [15:0] cpu_addr;
wire [7:0] cpu_dout;
wire cpu_rd;
wire cpu_wr;
apple1 apple1 apple1 apple1
( (
.reset(reset_button), .reset(reset_button),
@ -547,6 +555,8 @@ user_io (
/***************************************** @sdram *****************************************/ /***************************************** @sdram *****************************************/
/******************************************************************************************/ /******************************************************************************************/
/******************************************************************************************/ /******************************************************************************************/
wire [7:0] sdram_dout;
// SDRAM control signals // SDRAM control signals
assign SDRAM_CKE = 1'b1; assign SDRAM_CKE = 1'b1;
@ -568,11 +578,11 @@ sdram sdram (
.init ( !pll_locked ), .init ( !pll_locked ),
// cpu interface // cpu interface
.din ( sdram_din ), .din ( bus_din ),
.addr ( sdram_addr ), .addr ( bus_addr ),
.we ( sdram_wr ), .we ( bus_wr ),
.oe ( sdram_rd ), .oe ( bus_rd ),
.dout ( sdram_dout ) .dout ( sdram_dout )
); );
/******************************************************************************************/ /******************************************************************************************/
@ -596,6 +606,17 @@ clock clock(
.pixel_clken ( pixel_clken ) // output: pixel clock enable .pixel_clken ( pixel_clken ) // output: pixel clock enable
); );
/******************************************************************************************/
/******************************************************************************************/
/***************************************** @led *******************************************/
/******************************************************************************************/
/******************************************************************************************/
wire dummy = is_downloading && download_wr;
assign LED = ~dummy;
/******************************************************************************************/ /******************************************************************************************/
/******************************************************************************************/ /******************************************************************************************/
/***************************************** @vdp *******************************************/ /***************************************** @vdp *******************************************/
@ -626,8 +647,8 @@ always @(posedge vdp_clock) begin
vdp_ena <= ~vdp_ena; vdp_ena <= ~vdp_ena;
end end
wire csr = tms_cs & sdram_rd; wire csr = tms_cs & bus_rd;
wire csw = tms_cs & sdram_wr; wire csw = tms_cs & bus_wr;
wire tms_HS; wire tms_HS;
wire tms_VS; wire tms_VS;
@ -655,11 +676,11 @@ tms9918
// control signals // control signals
.csr_n ( ~csr ), .csr_n ( ~csr ),
.csw_n ( ~csw ), .csw_n ( ~csw ),
.mode ( sdram_addr[0] ), .mode ( bus_addr[0] ),
.int_n ( VDP_INT_n ), .int_n ( VDP_INT_n ),
// cpu I/O // cpu I/O
.cd_i ( sdram_din ), .cd_i ( bus_din ),
.cd_o ( vdp_dout ), .cd_o ( vdp_dout ),
// vram // vram
@ -694,9 +715,9 @@ sid_top sid_top
.clock(sys_clock), .clock(sys_clock),
.reset(reset_button), .reset(reset_button),
.addr(sdram_addr[7:0]), .addr(bus_addr[7:0]),
.wren(cpu_wr & sid_cs), .wren(cpu_wr & sid_cs),
.wdata(sdram_din), .wdata(bus_din),
.rdata(sid_dout), .rdata(sid_dout),
.potx(0), .potx(0),