Apple-1-HW
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Apple1_MiST
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remove surviving references to uart

This commit is contained in:
nino-porcino 2021-12-30 20:08:22 +01:00
parent 68846df5d0
commit dd52677652
2 changed files with 0 additions and 8 deletions
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4
rtl/apple1.v
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@ -26,10 +26,6 @@ module apple1(
input clk14, // 14 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation)
// I/O interface to computer
input uart_rx, // asynchronous serial data input from computer
output uart_tx, // asynchronous serial data output to computer
output uart_cts, // clear to send flag to computer
// RAM interface
output [15:0] ram_addr,
output [7:0] ram_din,

4
rtl/apple1_mist.sv
View File

@ -147,10 +147,6 @@ apple1 apple1
.clk14(clk14),
.rst_n(~reset_button),
.uart_rx(), // uart not connected
.uart_tx(), // uart not connected
.uart_cts(), // uart not connected
// RAM interface
.ram_addr (cpu_addr),
.ram_din (cpu_dout),