improve display accuracy

rtl/aci.v

@@ -21,7 +21,7 @@ module ACI (
 
 	wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
 	
-   wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & tape_in } : addr[7:0];
+   wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & debounced_tape_in } : addr[7:0];
 		
    always @(posedge clk) begin
 
@@ -30,6 +30,24 @@ module ACI (
 
       dout <= rom_data[read_addr];
    end
+	
+	// filters tape_in with anti bounce 
+	wire debounced_tape_in = last_tape_in;
+	reg last_tape_in;
+	reg [31:0] bounce_cnt;
+	localparam bounce_max = 3579;   // 57272719 / 3579 = ~16 KHz max
+	
+	always @(posedge clk) begin
+		if(tape_in != last_tape_in) begin			
+			if(bounce_cnt < bounce_max) begin
+				bounce_cnt <= bounce_cnt + 1;
+			end
+			else begin
+				bounce_cnt <= 0;				
+				last_tape_in = tape_in;		
+			end
+		end
+	end
 
 endmodule
     

rtl/apple1_mist.sv

@@ -170,8 +170,8 @@ downloader
    .ROM_done    ( ROM_loaded      ),	
 	         
    // external ram interface
-   .clk     ( sys_clock      ),
-	.clk_ena ( cpu_clken_noRF ),
+   .clk     ( cpu_clock      ), // does not work with sys_clock+cpu_clken_noRF and SDRAM
+	.clk_ena ( 1              ), // most likely because ioctl_wr isn't 1 for all the 8 sdram cycles
    .wr      ( download_wr    ),
    .addr    ( download_addr  ),
    .data    ( download_data  )	
@@ -277,7 +277,7 @@ wire        sdram_wr;
 wire        sdram_rd;
 wire [7:0]  sdram_dout;
 
-always @(*) begin
+always @(posedge sys_clock) begin
 	if(is_downloading && download_wr) begin
 		sdram_addr   <= download_addr;
 		sdram_din    <= download_data;
@@ -354,7 +354,7 @@ apple1 apple1
 	.reset(reset_button), 
 	
 	.sys_clock   ( sys_clock   ),  // system clock
-	.cpu_clken   ( cpu_clken   ),  // CPU clock enable	
+	.cpu_clken   ( cpu_clken & ~is_downloading ),  // CPU clock enable	
 	.pixel_clken ( pixel_clken ),  // pixel clock enable
 	
 	// RAM interface
@@ -550,35 +550,6 @@ user_io (
 // SDRAM control signals
 assign SDRAM_CKE = 1'b1;
 
-/*
-wire [24:0] sdram_addr;
-wire  [7:0] sdram_din;
-wire        sdram_wr;
-wire        sdram_rd;
-wire [7:0]  sdram_dout;
-
-always @(*) begin
-	if(is_downloading && download_wr) begin
-		sdram_addr   <= download_addr;
-		sdram_din    <= download_data;
-		sdram_wr     <= download_wr;
-		sdram_rd     <= 1'b1;			
-	end	
-	else if(eraser_busy) begin		
-		sdram_addr   <= eraser_addr;
-		sdram_din    <= eraser_data;
-		sdram_wr     <= eraser_wr;
-		sdram_rd     <= 1'b1;		
-	end	
-	else begin
-		sdram_addr   <= { 9'd0, cpu_addr[15:0] };
-		sdram_din    <= cpu_dout;		
-		sdram_wr     <= cpu_wr;
-		sdram_rd     <= cpu_rd;
-	end	
-end
-*/
-
 sdram sdram (
 	// interface to the MT48LC16M16 chip
    .sd_data        ( SDRAM_DQ                  ),

rtl/clock.v

@@ -40,7 +40,7 @@ localparam REFRESH_DIVISOR = 65;  // counts 65 clock ticks (one complete scanlin
 		end
 	end
 	
-	// the ram refresh cycle is activated by the horizontal counter on every 10 character
+	// the ram refresh cycle is activated by the horizontal counter on every 10 characters
 	wire RF = counter_refresh == 25 || counter_refresh == 35 || counter_refresh == 45 || counter_refresh == 55;
 	
 	assign cpu_clken      = counter_cpu   == 0 && !RF;

rtl/display.v

@@ -184,7 +184,7 @@ module display (
     assign cursor = {v_cursor, h_cursor};
     assign vram_r_addr = {vram_v_addr, vram_h_addr};
 	 
-	 wire [5:0] cursor_character = cursor_on ? 6'd0 : 6'd32;
+	 wire [5:0] cursor_character = cursor_on ? 6'd0 : 6'd32;   // "@" or space
 
     assign font_char = (vram_r_addr != cursor) ? vram_dout : cursor_character;
     assign font_pixel = h_dot;     
@@ -220,11 +220,12 @@ module display (
         else
         if(pixel_clken) begin
             vram_w_en <= 0;
+				
+				// accepts a new character only at the start of each frame
 				if(v_cnt == 0 && h_cnt == 0) 
 				   ready <= 1;
 
-            if (clr_screen)
-            begin
+            if(clr_screen) begin
                 // return to top of screen
                 h_cursor <= 6'd0;
                 v_cursor <= 5'd0;
@@ -237,55 +238,41 @@ module display (
                 vram_din <= 6'd32;
                 vram_w_en <= 1;
             end
-            else
-            begin
+            else begin
                 // cursor overflow handling
-                if (h_cursor == 6'd40)
-                begin
+                if (h_cursor == 6'd40) begin
                     h_cursor <= 6'd0;
                     v_cursor <= v_cursor + 'd1;
                 end
 
-                if (v_cursor == vram_end_addr)
-                begin
+                if (v_cursor == vram_end_addr) begin
                     vram_start_addr <= vram_start_addr + 'd1;
                     vram_end_addr <= vram_end_addr + 'd1;
                 end
 
-                if (address == 1'b0) // address low == TX register
-                begin
-                    if (cpu_clken & w_en & ready)
-                    begin
+					 // address low == TX register
+                if (address == 1'b0) begin
+                    if (cpu_clken & w_en & ready) begin
                         // incoming character                        
 					         ready <= 0;			
-
-                        case(din)
-                        8'h0D,
-                        8'h8D: begin
-                            // handle carriage return
-                            h_cursor <= 0;
-                            v_cursor <= v_cursor + 'd1;
-                        end
-
-                        8'h00,
-                        8'h0A,
-                        8'h9B,
-                        8'h7F: begin
-                            // ignore the escape key
-                            h_cursor <= 0;
-                        end
-
-                        default: begin
+								
+								if(din[6:0]=='h0D) begin
+									 // handle carriage return
+									 h_cursor <= 0;
+									 v_cursor <= v_cursor + 'd1;
+								end 
+								else if(din[6:0] < 32) begin
+								    // 0-31 non printable characters, do nothing
+								end								
+								else begin
                             vram_w_addr <= cursor;
                             vram_din <= {~din[6], din[4:0]};
                             vram_w_en <= 1;
                             h_cursor <= h_cursor + 1;
-                        end
-                        endcase
+                        end                        
                     end                    
                 end
-                else
-                begin
+                else begin
                     vram_w_addr <= {vram_clr_addr, vram_h_addr};
                     vram_din <= 6'd32;
                     vram_w_en <= 1;