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d24a1e174b |
20
rtl/aci.v
20
rtl/aci.v
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@ -21,7 +21,7 @@ module ACI (
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wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
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wire io_range = addr >= 16'hC000 && addr <= 16'hC0FF;
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wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & tape_in } : addr[7:0];
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wire [7:0] read_addr = io_range ? { addr[7:1], addr[0] & debounced_tape_in } : addr[7:0];
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always @(posedge clk) begin
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always @(posedge clk) begin
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@ -31,5 +31,23 @@ module ACI (
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dout <= rom_data[read_addr];
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dout <= rom_data[read_addr];
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end
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end
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// filters tape_in with anti bounce
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wire debounced_tape_in = last_tape_in;
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reg last_tape_in;
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reg [31:0] bounce_cnt;
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localparam bounce_max = 3579; // 57272719 / 3579 = ~16 KHz max
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always @(posedge clk) begin
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if(tape_in != last_tape_in) begin
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if(bounce_cnt < bounce_max) begin
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bounce_cnt <= bounce_cnt + 1;
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end
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else begin
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bounce_cnt <= 0;
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last_tape_in = tape_in;
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end
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end
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end
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endmodule
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endmodule
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@ -170,8 +170,8 @@ downloader
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.ROM_done ( ROM_loaded ),
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.ROM_done ( ROM_loaded ),
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// external ram interface
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// external ram interface
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.clk ( sys_clock ),
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.clk ( cpu_clock ), // does not work with sys_clock+cpu_clken_noRF and SDRAM
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.clk_ena ( cpu_clken_noRF ),
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.clk_ena ( 1 ), // most likely because ioctl_wr isn't 1 for all the 8 sdram cycles
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.wr ( download_wr ),
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.wr ( download_wr ),
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.addr ( download_addr ),
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.addr ( download_addr ),
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.data ( download_data )
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.data ( download_data )
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@ -277,7 +277,7 @@ wire sdram_wr;
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wire sdram_rd;
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wire sdram_rd;
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wire [7:0] sdram_dout;
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wire [7:0] sdram_dout;
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always @(*) begin
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always @(posedge sys_clock) begin
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if(is_downloading && download_wr) begin
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if(is_downloading && download_wr) begin
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sdram_addr <= download_addr;
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sdram_addr <= download_addr;
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sdram_din <= download_data;
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sdram_din <= download_data;
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@ -354,7 +354,7 @@ apple1 apple1
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.reset(reset_button),
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.reset(reset_button),
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.sys_clock ( sys_clock ), // system clock
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.sys_clock ( sys_clock ), // system clock
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.cpu_clken ( cpu_clken ), // CPU clock enable
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.cpu_clken ( cpu_clken & ~is_downloading ), // CPU clock enable
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.pixel_clken ( pixel_clken ), // pixel clock enable
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.pixel_clken ( pixel_clken ), // pixel clock enable
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// RAM interface
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// RAM interface
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@ -550,35 +550,6 @@ user_io (
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// SDRAM control signals
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// SDRAM control signals
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assign SDRAM_CKE = 1'b1;
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assign SDRAM_CKE = 1'b1;
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/*
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wire [24:0] sdram_addr;
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wire [7:0] sdram_din;
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wire sdram_wr;
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wire sdram_rd;
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wire [7:0] sdram_dout;
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always @(*) begin
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if(is_downloading && download_wr) begin
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sdram_addr <= download_addr;
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sdram_din <= download_data;
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sdram_wr <= download_wr;
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sdram_rd <= 1'b1;
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end
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else if(eraser_busy) begin
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sdram_addr <= eraser_addr;
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sdram_din <= eraser_data;
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sdram_wr <= eraser_wr;
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sdram_rd <= 1'b1;
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end
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else begin
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sdram_addr <= { 9'd0, cpu_addr[15:0] };
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sdram_din <= cpu_dout;
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sdram_wr <= cpu_wr;
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sdram_rd <= cpu_rd;
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end
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end
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*/
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sdram sdram (
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sdram sdram (
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// interface to the MT48LC16M16 chip
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// interface to the MT48LC16M16 chip
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.sd_data ( SDRAM_DQ ),
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.sd_data ( SDRAM_DQ ),
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@ -40,7 +40,7 @@ localparam REFRESH_DIVISOR = 65; // counts 65 clock ticks (one complete scanlin
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end
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end
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end
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end
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// the ram refresh cycle is activated by the horizontal counter on every 10 character
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// the ram refresh cycle is activated by the horizontal counter on every 10 characters
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wire RF = counter_refresh == 25 || counter_refresh == 35 || counter_refresh == 45 || counter_refresh == 55;
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wire RF = counter_refresh == 25 || counter_refresh == 35 || counter_refresh == 45 || counter_refresh == 55;
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assign cpu_clken = counter_cpu == 0 && !RF;
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assign cpu_clken = counter_cpu == 0 && !RF;
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@ -184,7 +184,7 @@ module display (
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assign cursor = {v_cursor, h_cursor};
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assign cursor = {v_cursor, h_cursor};
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assign vram_r_addr = {vram_v_addr, vram_h_addr};
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assign vram_r_addr = {vram_v_addr, vram_h_addr};
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wire [5:0] cursor_character = cursor_on ? 6'd0 : 6'd32;
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wire [5:0] cursor_character = cursor_on ? 6'd0 : 6'd32; // "@" or space
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assign font_char = (vram_r_addr != cursor) ? vram_dout : cursor_character;
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assign font_char = (vram_r_addr != cursor) ? vram_dout : cursor_character;
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assign font_pixel = h_dot;
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assign font_pixel = h_dot;
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@ -220,11 +220,12 @@ module display (
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else
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else
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if(pixel_clken) begin
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if(pixel_clken) begin
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vram_w_en <= 0;
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vram_w_en <= 0;
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// accepts a new character only at the start of each frame
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if(v_cnt == 0 && h_cnt == 0)
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if(v_cnt == 0 && h_cnt == 0)
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ready <= 1;
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ready <= 1;
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if (clr_screen)
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if(clr_screen) begin
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begin
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// return to top of screen
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// return to top of screen
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h_cursor <= 6'd0;
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h_cursor <= 6'd0;
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v_cursor <= 5'd0;
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v_cursor <= 5'd0;
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@ -237,55 +238,41 @@ module display (
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vram_din <= 6'd32;
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vram_din <= 6'd32;
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vram_w_en <= 1;
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vram_w_en <= 1;
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end
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end
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else
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else begin
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begin
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// cursor overflow handling
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// cursor overflow handling
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if (h_cursor == 6'd40)
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if (h_cursor == 6'd40) begin
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begin
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h_cursor <= 6'd0;
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h_cursor <= 6'd0;
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v_cursor <= v_cursor + 'd1;
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v_cursor <= v_cursor + 'd1;
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end
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end
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if (v_cursor == vram_end_addr)
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if (v_cursor == vram_end_addr) begin
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begin
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vram_start_addr <= vram_start_addr + 'd1;
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vram_start_addr <= vram_start_addr + 'd1;
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vram_end_addr <= vram_end_addr + 'd1;
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vram_end_addr <= vram_end_addr + 'd1;
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end
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end
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if (address == 1'b0) // address low == TX register
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// address low == TX register
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begin
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if (address == 1'b0) begin
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if (cpu_clken & w_en & ready)
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if (cpu_clken & w_en & ready) begin
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begin
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// incoming character
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// incoming character
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ready <= 0;
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ready <= 0;
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case(din)
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if(din[6:0]=='h0D) begin
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8'h0D,
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8'h8D: begin
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// handle carriage return
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// handle carriage return
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h_cursor <= 0;
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h_cursor <= 0;
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v_cursor <= v_cursor + 'd1;
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v_cursor <= v_cursor + 'd1;
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end
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end
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else if(din[6:0] < 32) begin
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8'h00,
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// 0-31 non printable characters, do nothing
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8'h0A,
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8'h9B,
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8'h7F: begin
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// ignore the escape key
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h_cursor <= 0;
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end
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end
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else begin
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default: begin
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vram_w_addr <= cursor;
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vram_w_addr <= cursor;
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vram_din <= {~din[6], din[4:0]};
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vram_din <= {~din[6], din[4:0]};
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vram_w_en <= 1;
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vram_w_en <= 1;
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h_cursor <= h_cursor + 1;
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h_cursor <= h_cursor + 1;
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end
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end
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endcase
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end
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end
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end
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end
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else
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else begin
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begin
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vram_w_addr <= {vram_clr_addr, vram_h_addr};
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vram_w_addr <= {vram_clr_addr, vram_h_addr};
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vram_din <= 6'd32;
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vram_din <= 6'd32;
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vram_w_en <= 1;
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vram_w_en <= 1;
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