192 lines
8.6 KiB
Plaintext
192 lines
8.6 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 11:23:36 April 10, 2018
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# apple-one_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:11:27 JANUARY 26, 2018"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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# Classic Timing Assignments
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# ==========================
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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# Analysis & Synthesis Assignments
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# ================================
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name TOP_LEVEL_ENTITY apple1_mist
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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# EDA Netlist Writer Assignments
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# ==============================
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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# Assembler Assignments
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# =====================
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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set_global_assignment -name GENERATE_RBF_FILE ON
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# Power Estimation Assignments
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# ============================
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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# Advanced I/O Timing Assignments
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# ===============================
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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# start EDA_TOOL_SETTINGS(eda_simulation)
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# ---------------------------------------
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# EDA Netlist Writer Assignments
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# ==============================
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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# end EDA_TOOL_SETTINGS(eda_simulation)
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# -------------------------------------
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
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# ===================================
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# Pin & Location Assignments
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# ==========================
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set_location_assignment PIN_7 -to LED
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set_location_assignment PIN_54 -to CLOCK_27
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set_location_assignment PIN_144 -to VGA_R[5]
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set_location_assignment PIN_143 -to VGA_R[4]
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set_location_assignment PIN_142 -to VGA_R[3]
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set_location_assignment PIN_141 -to VGA_R[2]
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set_location_assignment PIN_137 -to VGA_R[1]
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set_location_assignment PIN_135 -to VGA_R[0]
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set_location_assignment PIN_133 -to VGA_B[5]
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set_location_assignment PIN_132 -to VGA_B[4]
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set_location_assignment PIN_125 -to VGA_B[3]
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set_location_assignment PIN_121 -to VGA_B[2]
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set_location_assignment PIN_120 -to VGA_B[1]
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set_location_assignment PIN_115 -to VGA_B[0]
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set_location_assignment PIN_114 -to VGA_G[5]
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set_location_assignment PIN_113 -to VGA_G[4]
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set_location_assignment PIN_112 -to VGA_G[3]
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set_location_assignment PIN_111 -to VGA_G[2]
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set_location_assignment PIN_110 -to VGA_G[1]
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set_location_assignment PIN_106 -to VGA_G[0]
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set_location_assignment PIN_136 -to VGA_VS
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set_location_assignment PIN_119 -to VGA_HS
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set_location_assignment PIN_65 -to AUDIO_L
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set_location_assignment PIN_80 -to AUDIO_R
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set_location_assignment PIN_105 -to SPI_DO
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set_location_assignment PIN_88 -to SPI_DI
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set_location_assignment PIN_126 -to SPI_SCK
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set_location_assignment PIN_127 -to SPI_SS2
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set_location_assignment PIN_91 -to SPI_SS3
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set_location_assignment PIN_13 -to CONF_DATA0
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set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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# end ENTITY(apple1_mist)
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# -----------------------
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/user_io.v"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/sd_card.v"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/scandoubler.v"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/rgb2ypbpr.v"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/osd.v"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/mist_video.v"
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set_global_assignment -name QIP_FILE "rtl/mist-modules/mist_core.qip"
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set_global_assignment -name VHDL_FILE "rtl/mist-modules/mist.vhd"
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set_global_assignment -name QIP_FILE "rtl/mist-modules/mist.qip"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/data_io.v"
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set_global_assignment -name VHDL_FILE "rtl/mist-modules/dac.vhd"
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set_global_assignment -name SYSTEMVERILOG_FILE "rtl/mist-modules/cofi.sv"
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set_global_assignment -name VERILOG_FILE "rtl/mist-modules/arcade_inputs.v"
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set_global_assignment -name VERILOG_FILE rtl/arlet_6502/cpu.v
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set_global_assignment -name VERILOG_FILE rtl/arlet_6502/ALU.v
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set_global_assignment -name VERILOG_FILE rtl/arlet_6502/arlet_6502.v
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set_global_assignment -name VERILOG_FILE rtl/apple1.v
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set_global_assignment -name VERILOG_FILE rtl/clock.v
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set_global_assignment -name VERILOG_FILE rtl/pwr_reset.v
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set_global_assignment -name VERILOG_FILE rtl/ram.v
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set_global_assignment -name VERILOG_FILE rtl/rom_basic.v
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set_global_assignment -name VERILOG_FILE rtl/rom_wozmon.v
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set_global_assignment -name VERILOG_FILE rtl/vram.v
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set_global_assignment -name VERILOG_FILE rtl/uart.v
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set_global_assignment -name VERILOG_FILE rtl/ps2keyboard.v
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set_global_assignment -name VERILOG_FILE rtl/vga.v
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set_global_assignment -name VERILOG_FILE rtl/async_tx_rx.v
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set_global_assignment -name VERILOG_FILE rtl/font_rom.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
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set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
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set_global_assignment -name QIP_FILE rtl/pll.qip
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set_global_assignment -name VERILOG_FILE rtl/osd.v
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set_global_assignment -name VERILOG_FILE rtl/mist_io.v
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/apple1_mist.sv
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |