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README.md

Apple1_MIST

Apple1 implementation for the MiST FPGA.

This was forked from Gehstock's project.

CHANGELOG

2021-12-28

  • 15 kHz video output (NTSC) and use of MiST scandoubler/video pipeline
  • more accurate 7x8 character matrix (5x7 + hardware spacing)
  • clock is now derived from 14.31818 instead of 25 MHz (more accurate)
  • serial port communication feature is disabled/removed
Description
apple1 for MiST FPGA
Readme 2.5 MiB
Languages
VHDL 51.6%
Verilog 37.9%
SystemVerilog 8.9%
xBase 1.3%
Tcl 0.2%
Other 0.1%