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https://github.com/nippur72/Apple1_MiST.git
synced 2025-02-28 18:29:27 +00:00
extend ram to 48 K
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commit
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@ -20,6 +20,7 @@
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// TODO special expansion boards: TMS9918, SID
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// TODO ascii keyboard
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// TODO check diff with updated data_io.v
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// TODO ram + display powerup initial values
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module apple1_mist(
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input CLOCK_27,
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@ -172,7 +173,7 @@ downloader
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// RAM
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ram ram(
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.clk (clk14 ),
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.address(sdram_addr[12:0]),
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.address(sdram_addr[15:0]),
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.w_en (sdram_wr ),
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.din (sdram_din ),
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.dout (sdram_dout)
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@ -205,7 +206,7 @@ always @(*) begin
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end
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*/
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else begin
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sdram_addr <= { 12'b0, cpu_addr[12:0] };
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sdram_addr <= { 9'b0, cpu_addr[15:0] };
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sdram_din <= cpu_dout;
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sdram_wr <= cpu_wr;
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sdram_rd <= cpu_rd;
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@ -236,9 +237,9 @@ wire [7:0] cpu_dout;
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wire cpu_rd;
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wire cpu_wr;
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wire ram_cs = (cpu_addr[15:13] == 3'b000); // 0x0000 -> 0x1FFF
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wire basic_cs = (cpu_addr[15:12] == 4'b1110); // 0xE000 -> 0xEFFF
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wire rom_cs = (cpu_addr[15:8] == 8'b11111111); // 0xFF00 -> 0xFFFF
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wire ram_cs = cpu_addr < 16'hc000; // (cpu_addr[15:13] == 3'b000); // 0x0000 -> 0x1FFF
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wire basic_cs = cpu_addr >= 16'hE000 && cpu_addr <= 16'hEFFF; // (cpu_addr[15:12] == 4'b1110); // 0xE000 -> 0xEFFF
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wire rom_cs = cpu_addr >= 16'hFF00 && cpu_addr <= 16'hFFFF; // (cpu_addr[15:8] == 8'b11111111); // 0xFF00 -> 0xFFFF
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wire [7:0] bus_dout = basic_cs ? basic_dout :
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rom_cs ? rom_dout :
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@ -24,16 +24,16 @@
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module ram (
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input clk, // clock signal
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input [12:0] address, // address bus
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input [15:0] address, // address bus
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input w_en, // active high write enable strobe
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input [7:0] din, // 8-bit data bus (input)
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output reg [7:0] dout // 8-bit data bus (output)
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);
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reg [7:0] ram_data[0:8191];
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reg [7:0] ram_data[0:49151];
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initial
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$readmemh("roms/ram.hex", ram_data, 0, 8191);
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//initial
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// $readmemh("roms/ram.hex", ram_data, 0, 8191);
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always @(posedge clk)
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begin
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