Apple-1-HW/RC6502-Apple-1-Replica
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RC6502-Apple-1-Replica/RC6502 VDU/RC6502 VDU.kicad_pcb

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Fixed footprint error
2018-12-04 20:36:13 +00:00
(kicad_pcb (version 4) (host pcbnew 4.0.7)
(general
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(links 195)
(no_connects 86)
(area 50.73 44.11 164.0554 154.579048)
Fixed footprint error
2018-12-04 20:36:13 +00:00
(thickness 1.6)
(drawings 4)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(tracks 706)
Fixed footprint error
2018-12-04 20:36:13 +00:00
(zones 0)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(modules 33)
(nets 87)
Fixed footprint error
2018-12-04 20:36:13 +00:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements 7FFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC)
(net 2 A15)
(net 3 A14)
(net 4 A13)
(net 5 A12)
(net 6 A11)
(net 7 A10)
(net 8 A9)
(net 9 A8)
(net 10 A7)
(net 11 A6)
(net 12 A5)
(net 13 A4)
(net 14 A3)
(net 15 A2)
(net 16 A1)
(net 17 A0)
(net 18 PHI2)
(net 19 PHI0)
(net 20 "Net-(J1-Pad22)")
(net 21 R/~W)
(net 22 D0)
(net 23 D1)
(net 24 D2)
(net 25 D3)
(net 26 D4)
(net 27 D5)
(net 28 D6)
(net 29 D7)
(net 30 "Net-(J2-Pad1)")
(net 31 VDU_BASE)
(net 32 "Net-(J2-Pad3)")
(net 33 "Net-(J2-Pad5)")
(net 34 "Net-(J2-Pad7)")
(net 35 "Net-(J2-Pad9)")
(net 36 "Net-(J3-Pad1)")
(net 37 "Net-(J3-Pad2)")
(net 38 "Net-(J3-Pad3)")
(net 39 Y)
(net 40 VDU_CLK)
(net 41 "Net-(J8-Pad2)")
(net 42 ~VDU_DISABLE)
(net 43 ~FS)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 44 VA12)
(net 45 VD6)
(net 46 VA0)
(net 47 VD0)
(net 48 VA1)
(net 49 VD1)
(net 50 VA2)
(net 51 VD2)
(net 52 VA3)
(net 53 VD3)
(net 54 VA4)
(net 55 VD4)
(net 56 GM2)
(net 57 VD5)
(net 58 GM1)
(net 59 GM0)
(net 60 VD7)
(net 61 VA5)
(net 62 VA6)
(net 63 S/~A)
(net 64 VA7)
(net 65 G/~A)
(net 66 VA8)
(net 67 VA9)
(net 68 VA10)
(net 69 CSS)
(net 70 VA11)
(net 71 VA14)
(net 72 VA13)
(net 73 RAM_RW)
(net 74 ~CS_RAM_EXT)
(net 75 ~CS_CTRL_EXT)
(net 76 "Net-(U8-Pad2)")
(net 77 ~VDU_WRITE)
(net 78 "Net-(U8-Pad10)")
(net 79 "Net-(U10-Pad2)")
(net 80 "Net-(U8-Pad5)")
(net 81 "Net-(U10-Pad1)")
(net 82 "Net-(U8-Pad6)")
(net 83 ~VDU_CTRL)
(net 84 "Net-(U10-Pad12)")
(net 85 "Net-(U10-Pad13)")
(net 86 GND)
Fixed footprint error
2018-12-04 20:36:13 +00:00
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(add_net A0)
(add_net A1)
(add_net A10)
(add_net A11)
(add_net A12)
(add_net A13)
(add_net A14)
(add_net A15)
(add_net A2)
(add_net A3)
(add_net A4)
(add_net A5)
(add_net A6)
(add_net A7)
(add_net A8)
(add_net A9)
(add_net CSS)
(add_net D0)
(add_net D1)
(add_net D2)
(add_net D3)
(add_net D4)
(add_net D5)
(add_net D6)
(add_net D7)
(add_net G/~A)
(add_net GM0)
(add_net GM1)
(add_net GM2)
(add_net GND)
(add_net "Net-(J1-Pad22)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J2-Pad3)")
(add_net "Net-(J2-Pad5)")
(add_net "Net-(J2-Pad7)")
(add_net "Net-(J2-Pad9)")
(add_net "Net-(J3-Pad1)")
(add_net "Net-(J3-Pad2)")
(add_net "Net-(J3-Pad3)")
(add_net "Net-(J8-Pad2)")
(add_net "Net-(U10-Pad1)")
(add_net "Net-(U10-Pad12)")
(add_net "Net-(U10-Pad13)")
(add_net "Net-(U10-Pad2)")
(add_net "Net-(U8-Pad10)")
(add_net "Net-(U8-Pad2)")
(add_net "Net-(U8-Pad5)")
(add_net "Net-(U8-Pad6)")
(add_net PHI0)
(add_net PHI2)
(add_net R/~W)
(add_net RAM_RW)
(add_net S/~A)
(add_net VA0)
(add_net VA1)
(add_net VA10)
(add_net VA11)
(add_net VA12)
(add_net VA13)
(add_net VA14)
(add_net VA2)
(add_net VA3)
(add_net VA4)
(add_net VA5)
(add_net VA6)
(add_net VA7)
(add_net VA8)
(add_net VA9)
(add_net VCC)
(add_net VD0)
(add_net VD1)
(add_net VD2)
(add_net VD3)
(add_net VD4)
(add_net VD5)
(add_net VD6)
(add_net VD7)
(add_net VDU_BASE)
(add_net VDU_CLK)
(add_net Y)
(add_net ~CS_CTRL_EXT)
(add_net ~CS_RAM_EXT)
(add_net ~FS)
(add_net ~VDU_CTRL)
(add_net ~VDU_DISABLE)
(add_net ~VDU_WRITE)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F62F) (tstamp 5C06E624)
(at 58.42 90.805 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C04594D)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C1 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F608) (tstamp 5C06E62A)
(at 104.14 65.405 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C04594C)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C2 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06FC2F) (tstamp 5C06E630)
(at 127.635 111.125 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C04594B)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C3 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at 2.5 2.56 270) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F186) (tstamp 5C06E636)
(at 112.395 111.125 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C04594A)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C4 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F677) (tstamp 5C06E63C)
(at 88.9 111.125 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C045949)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C5 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F65E) (tstamp 5C06E642)
(at 73.66 111.125 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C045948)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C6 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F404) (tstamp 5C06E648)
(at 142.875 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C045947)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C7 (at 2.54 0) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at 2.54 -2.54) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.5 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(pad 2 thru_hole circle (at 5 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F348) (tstamp 5C06E64E)
(at 119.38 83.185 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C045950)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C8 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F308) (tstamp 5C06E654)
(at 134.62 83.185 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C0C5965)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C9 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Capacitors_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm (layer F.Cu) (tedit 5C06F2DB) (tstamp 5C06E65A)
(at 149.86 83.185 270)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "C, Disc series, Radial, pin pitch=5.00mm, , diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
(path /5C0C59F4)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference C10 (at 2.54 0 360) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value 100nF (at -1.905 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.15 -1.25) (end 0.15 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.15 1.25) (end 4.85 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 1.25) (end 4.85 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.85 -1.25) (end 0.15 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.09 -1.31) (end 4.91 -1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 1.31) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 -1.31) (end 0.09 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 0.09 0.996) (end 0.09 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 -1.31) (end 4.91 -0.996) (layer F.SilkS) (width 0.12))
(fp_line (start 4.91 0.996) (end 4.91 1.31) (layer F.SilkS) (width 0.12))
(fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.05 1.6) (end 6.05 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 1.6) (end 6.05 -1.6) (layer F.CrtYd) (width 0.05))
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Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 2.5 0 360) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
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Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole circle (at 5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Disc_D4.7mm_W2.5mm_P5.00mm.wrl
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(descr "Through hole angled pin header, 1x39, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x39 2.54mm single row")
(path /5C0478BD)
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(fp_line (start 1.042929 68.2) (end 1.44 68.2) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.042929 74.04) (end 1.44 74.04) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 74.93) (end 4.1 74.93) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 75.82) (end 10.1 75.82) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 75.82) (end 10.1 76.58) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 76.58) (end 4.1 76.58) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 75.82) (end 1.44 75.82) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 76.58) (end 1.44 76.58) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 77.47) (end 4.1 77.47) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 78.36) (end 10.1 78.36) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 78.36) (end 10.1 79.12) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 79.12) (end 4.1 79.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 78.36) (end 1.44 78.36) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 79.12) (end 1.44 79.12) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 80.01) (end 4.1 80.01) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 80.9) (end 10.1 80.9) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 80.9) (end 10.1 81.66) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 81.66) (end 4.1 81.66) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 80.9) (end 1.44 80.9) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 81.66) (end 1.44 81.66) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 82.55) (end 4.1 82.55) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 83.44) (end 10.1 83.44) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 83.44) (end 10.1 84.2) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 84.2) (end 4.1 84.2) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 83.44) (end 1.44 83.44) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 84.2) (end 1.44 84.2) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 85.09) (end 4.1 85.09) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 85.98) (end 10.1 85.98) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 85.98) (end 10.1 86.74) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 86.74) (end 4.1 86.74) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 85.98) (end 1.44 85.98) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 86.74) (end 1.44 86.74) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 87.63) (end 4.1 87.63) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 88.52) (end 10.1 88.52) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 88.52) (end 10.1 89.28) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 89.28) (end 4.1 89.28) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 88.52) (end 1.44 88.52) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 89.28) (end 1.44 89.28) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 90.17) (end 4.1 90.17) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 91.06) (end 10.1 91.06) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 91.06) (end 10.1 91.82) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 91.82) (end 4.1 91.82) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 91.06) (end 1.44 91.06) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 91.82) (end 1.44 91.82) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 92.71) (end 4.1 92.71) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 93.6) (end 10.1 93.6) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 93.6) (end 10.1 94.36) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 94.36) (end 4.1 94.36) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 93.6) (end 1.44 93.6) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 94.36) (end 1.44 94.36) (layer F.SilkS) (width 0.12))
(fp_line (start 1.44 95.25) (end 4.1 95.25) (layer F.SilkS) (width 0.12))
(fp_line (start 4.1 96.14) (end 10.1 96.14) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 96.14) (end 10.1 96.9) (layer F.SilkS) (width 0.12))
(fp_line (start 10.1 96.9) (end 4.1 96.9) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 96.14) (end 1.44 96.14) (layer F.SilkS) (width 0.12))
(fp_line (start 1.042929 96.9) (end 1.44 96.9) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -1.27) (end 0 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 98.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 98.3) (end 10.55 98.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.55 98.3) (end 10.55 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 10.55 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.77 48.26 360) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 2 A15))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 A14))
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 A13))
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 A12))
(pad 5 thru_hole oval (at 0 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 A11))
(pad 6 thru_hole oval (at 0 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 A10))
(pad 7 thru_hole oval (at 0 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 A9))
(pad 8 thru_hole oval (at 0 17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 A8))
(pad 9 thru_hole oval (at 0 20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 A7))
(pad 10 thru_hole oval (at 0 22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 A6))
(pad 11 thru_hole oval (at 0 25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 A5))
(pad 12 thru_hole oval (at 0 27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 A4))
(pad 13 thru_hole oval (at 0 30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 A3))
(pad 14 thru_hole oval (at 0 33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 A2))
(pad 15 thru_hole oval (at 0 35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 A1))
(pad 16 thru_hole oval (at 0 38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 A0))
(pad 17 thru_hole oval (at 0 40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 18 thru_hole oval (at 0 43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 VCC))
(pad 19 thru_hole oval (at 0 45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 PHI2))
(pad 20 thru_hole oval (at 0 48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 21 thru_hole oval (at 0 50.8 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 19 PHI0))
(pad 22 thru_hole oval (at 0 53.34 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 20 "Net-(J1-Pad22)"))
(pad 23 thru_hole oval (at 0 55.88 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 24 thru_hole oval (at 0 58.42 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 R/~W))
(pad 25 thru_hole oval (at 0 60.96 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 26 thru_hole oval (at 0 63.5 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 27 thru_hole oval (at 0 66.04 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 22 D0))
(pad 28 thru_hole oval (at 0 68.58 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 D1))
(pad 29 thru_hole oval (at 0 71.12 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 24 D2))
(pad 30 thru_hole oval (at 0 73.66 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 D3))
(pad 31 thru_hole oval (at 0 76.2 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 D4))
(pad 32 thru_hole oval (at 0 78.74 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 D5))
(pad 33 thru_hole oval (at 0 81.28 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 28 D6))
(pad 34 thru_hole oval (at 0 83.82 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 29 D7))
(pad 35 thru_hole oval (at 0 86.36 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 36 thru_hole oval (at 0 88.9 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 37 thru_hole oval (at 0 91.44 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 38 thru_hole oval (at 0 93.98 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 39 thru_hole oval (at 0 96.52 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x39_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module mounting:Mounting (layer F.Cu) (tedit 594143BA) (tstamp 5C06E6A1)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(at 57.15 48.895)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /5C045951)
(fp_text reference J4 (at 0 -3.81) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole (at 0 3.81) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
)
(module mounting:Mounting (layer F.Cu) (tedit 594143BA) (tstamp 5C06E6A6)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(at 57.15 137.16)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /5C045953)
(fp_text reference J5 (at 0 -3.81) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole (at 0 3.81) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
)
(module mounting:Mounting (layer F.Cu) (tedit 594143BA) (tstamp 5C06E6AB)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(at 147.32 137.16)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /5C045952)
(fp_text reference J6 (at 0 -3.81) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole (at 0 3.81) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
)
(module mounting:Mounting (layer F.Cu) (tedit 594143BA) (tstamp 5C06E6B0)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(at 147.32 48.895)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "module 1 pin (ou trou mecanique de percage)")
(tags DEV)
(path /5C045954)
(fp_text reference J7 (at 0 -3.81) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Hole (at 0 3.81) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2 0.8) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 2.6 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 0 -2.286) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole circle (at 0 0) (size 5 5) (drill 3.2) (layers *.Cu *.Mask))
)
(module rca:rca_yellow (layer F.Cu) (tedit 593D80CA) (tstamp 5C06E6B7)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(at 146.685 57.15 90)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "RCA Audio connector, yellow, Pro Signal p/n PSG01547")
(tags "rca, audio")
(path /5C0DE558)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference J8 (at 0 15.7988 90) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (thickness 0.3048)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value RCA_PLUG (at 0 -8.89 90) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (thickness 0.3048)))
)
(fp_circle (center -3.2512 -5.79882) (end -3.79984 -5.79882) (layer F.SilkS) (width 0.381))
(fp_circle (center 3.2512 -5.79882) (end 2.70002 -5.84962) (layer F.SilkS) (width 0.381))
(fp_circle (center 3.2512 4.0005) (end 2.70002 4.04876) (layer F.SilkS) (width 0.381))
(fp_circle (center -3.2512 4.0005) (end -3.79984 3.9497) (layer F.SilkS) (width 0.381))
(fp_circle (center -3.2512 0) (end -3.79984 0) (layer F.SilkS) (width 0.381))
(fp_circle (center 3.2512 0) (end 2.70002 -0.0508) (layer F.SilkS) (width 0.381))
(fp_line (start -4.30022 5.00126) (end -4.30022 14.00048) (layer F.SilkS) (width 0.381))
(fp_line (start -4.30022 14.00048) (end 4.30022 14.00048) (layer F.SilkS) (width 0.381))
(fp_line (start 4.30022 14.00048) (end 4.30022 5.00126) (layer F.SilkS) (width 0.381))
(fp_line (start 4.8006 -4.89966) (end 5.40004 -4.89966) (layer F.SilkS) (width 0.381))
(fp_line (start 5.40004 -4.89966) (end 5.40004 -3.0988) (layer F.SilkS) (width 0.381))
(fp_line (start 5.40004 -3.0988) (end 4.8006 -3.0988) (layer F.SilkS) (width 0.381))
(fp_line (start -5.40004 -4.89966) (end -4.8006 -4.89966) (layer F.SilkS) (width 0.381))
(fp_line (start -4.8006 -3.0988) (end -5.40004 -3.0988) (layer F.SilkS) (width 0.381))
(fp_line (start -5.40004 -3.0988) (end -5.40004 -4.89966) (layer F.SilkS) (width 0.381))
(fp_line (start -4.8006 -6.79958) (end -1.80086 -6.79958) (layer F.SilkS) (width 0.381))
(fp_line (start -1.80086 -6.79958) (end -1.80086 -5.99948) (layer F.SilkS) (width 0.381))
(fp_line (start -1.80086 -5.99948) (end 1.80086 -5.99948) (layer F.SilkS) (width 0.381))
(fp_line (start 1.80086 -5.99948) (end 1.80086 -6.79958) (layer F.SilkS) (width 0.381))
(fp_line (start 1.80086 -6.79958) (end 4.8006 -6.79958) (layer F.SilkS) (width 0.381))
(fp_line (start 4.8006 5.00126) (end -4.8006 5.00126) (layer F.SilkS) (width 0.381))
(fp_line (start -4.8006 4.99872) (end -4.8006 -6.80212) (layer F.SilkS) (width 0.381))
(fp_line (start 4.8006 -6.79958) (end 4.8006 5.00126) (layer F.SilkS) (width 0.381))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole oval (at 3.81 -3.81 90) (size 1.99898 3.19786) (drill oval 0.99568 2.1971) (layers *.Cu *.Mask F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 41 "Net-(J8-Pad2)"))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole oval (at 0 -1.27 90) (size 3.19786 1.99898) (drill oval 2.1971 0.99568) (layers *.Cu *.Mask F.SilkS)
(net 86 GND))
(pad 2 thru_hole oval (at -3.81 -3.81 90) (size 1.99898 3.19786) (drill oval 0.99568 2.1971) (layers *.Cu *.Mask F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 41 "Net-(J8-Pad2)"))
(model walter/conn_av/rca_yellow.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFCE) (tstamp 5C06E6BD)
(at 111.76 48.26 90)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /5C086A5B)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference JP1 (at 0 -2.54 270) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value VDU_EN (at 2.54 1.27 180) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 0 -2.54 90) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 31 VDU_BASE))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 42 ~VDU_DISABLE))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFCC) (tstamp 5C06E6C3)
(at 111.76 54.61 90)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /5C05E5BB)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference JP2 (at 0 -2.54 270) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value PHI0_OUT (at 2.54 1.27 180) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 0 -2.54 270) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 40 VDU_CLK))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 19 PHI0))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C06EFDA) (tstamp 5C06E6C9)
(at 121.92 54.61 90)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(path /5C0D03FF)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference JP3 (at 0 -2.54 270) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value INT_ON_FS (at 2.54 1.27 180) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 0 -2.54 270) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 43 ~FS))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 20 "Net-(J1-Pad22)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-40_W15.24mm_Socket (layer F.Cu) (tedit 5C06F4B1) (tstamp 5C06E737)
(at 62.23 50.165)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "40-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket")
(path /5C053F7E)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U1 (at 7.62 24.13) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MC6847 (at 7.62 50.59) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 49.53) (end 0.255 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 49.53) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 49.59) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 49.59) (end 16.51 49.59) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 49.59) (end 16.51 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 49.59) (end 14.08 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 49.59) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 49.65) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 49.65) (end 16.57 49.65) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 49.65) (end 16.57 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.55 -1.6) (end -1.55 49.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 49.85) (end 16.8 49.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 49.85) (end 16.8 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.62 24.13) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 21 thru_hole oval (at 15.24 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 44 VA12))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 45 VD6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 22 thru_hole oval (at 15.24 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 46 VA0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 47 VD0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 23 thru_hole oval (at 15.24 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 48 VA1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 49 VD1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 24 thru_hole oval (at 15.24 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 50 VA2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 51 VD2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 25 thru_hole oval (at 15.24 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 52 VA3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 53 VD3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 26 thru_hole oval (at 15.24 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 54 VA4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 55 VD4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 27 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 56 GM2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 57 VD5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 28 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 Y))
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 "Net-(J3-Pad1)"))
(pad 29 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 58 GM1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 "Net-(J3-Pad2)"))
(pad 30 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 59 GM0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 38 "Net-(J3-Pad3)"))
(pad 31 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 42 ~VDU_DISABLE))
(pad 32 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 60 VD7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 61 VA5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 33 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 40 VDU_CLK))
(pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 62 VA6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 34 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 63 S/~A))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 64 VA7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 35 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 65 G/~A))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 66 VA8))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 36 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(pad 37 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 43 ~FS))
(pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 67 VA9))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 38 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 68 VA10))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 39 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 69 CSS))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 70 VA11))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 40 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 60 VD7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-40_W15.24mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-28_W15.24mm_Socket (layer F.Cu) (tedit 5C06F4B5) (tstamp 5C06E757)
(at 85.09 65.405)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "28-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 15.24mm 600mil Socket")
(path /5C045929)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U2 (at 7.62 16.51) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value HM62256BLP-7 (at 7.62 35.35) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 7.62 -1.33) (end 6.62 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.255 -1.27) (end 14.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 -1.27) (end 14.985 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 14.985 34.29) (end 0.255 34.29) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 34.29) (end 0.255 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 34.35) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 34.35) (end 16.51 34.35) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 34.35) (end 16.51 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 16.51 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 6.62 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 34.35) (end 14.08 34.35) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 34.35) (end 14.08 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 14.08 -1.33) (end 8.62 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 34.41) (end 16.57 34.41) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 34.41) (end 16.57 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 16.57 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.55 -1.6) (end -1.55 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 34.65) (end 16.8 34.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 34.65) (end 16.8 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.8 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.62 16.51) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 71 VA14))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 15.24 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 53 VD3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 44 VA12))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 16 thru_hole oval (at 15.24 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 55 VD4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 64 VA7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 17 thru_hole oval (at 15.24 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 57 VD5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 62 VA6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 18 thru_hole oval (at 15.24 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 45 VD6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 61 VA5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 19 thru_hole oval (at 15.24 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 60 VD7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 54 VA4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 15.24 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 52 VA3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 21 thru_hole oval (at 15.24 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 68 VA10))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 50 VA2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 22 thru_hole oval (at 15.24 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 48 VA1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 23 thru_hole oval (at 15.24 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 70 VA11))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 46 VA0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 24 thru_hole oval (at 15.24 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 67 VA9))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 47 VD0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 25 thru_hole oval (at 15.24 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 66 VA8))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 49 VD1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 26 thru_hole oval (at 15.24 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 72 VA13))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 51 VD2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 27 thru_hole oval (at 15.24 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 73 RAM_RW))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 28 thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-28_W15.24mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5C06F4A4) (tstamp 5C06E76F)
(at 116.205 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C056659)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U3 (at 3.81 11.43) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS244 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 A12))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 9 A8))
(pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 70 VA11))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 A13))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 8 A9))
(pad 14 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 68 VA10))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 71 VA14))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 A14))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 A10))
(pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 67 VA9))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 72 VA13))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 17 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 A15))
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 A11))
(pad 18 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 66 VA8))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 44 VA12))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 19 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5C06F49F) (tstamp 5C06E787)
(at 100.965 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C055918)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U4 (at 3.81 11.43) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS244 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 A4))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 A0))
(pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 52 VA3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 64 VA7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 12 A5))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 A1))
(pad 14 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 50 VA2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 62 VA6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 A6))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 15 A2))
(pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 48 VA1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 61 VA5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 17 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 A7))
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 A3))
(pad 18 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 46 VA0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 54 VA4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 19 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5C06F4A8) (tstamp 5C06E79F)
(at 77.47 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C057ABB)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U5 (at 3.81 11.43) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS245 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 73 RAM_RW))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 D0))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 60 VD7))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 D1))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 45 VD6))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 D2))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 57 VD5))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 14 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 D3))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 55 VD4))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 D4))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 53 VD3))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 D5))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 51 VD2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 17 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 D6))
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 49 VD1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 18 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 D7))
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 47 VD0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 19 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-20_W7.62mm (layer F.Cu) (tedit 5C06F4AB) (tstamp 5C06E7B7)
(at 62.23 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "20-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C049977)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U6 (at 3.81 11.43) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS374 (at 3.81 25.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 24.13) (end 0.635 24.13) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 24.13) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 24.19) (end 6.46 24.19) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 24.19) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 24.4) (end 8.7 24.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 24.4) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 11.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 75 ~CS_CTRL_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 72 VA13))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 56 GM2))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 D0))
(pad 13 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 D4))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 D1))
(pad 14 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 D5))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 71 VA14))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 15 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 58 GM1))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 65 G/~A))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 16 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 59 GM0))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 24 D2))
(pad 17 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 28 D6))
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 25 D3))
(pad 18 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 D7))
(pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 63 S/~A))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 19 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 69 CSS))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 20 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-20_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-16_W7.62mm_Socket (layer F.Cu) (tedit 5C06F49C) (tstamp 5C06E7CB)
(at 131.445 111.125)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
(path /5C045924)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U7 (at 3.81 8.89) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74HCT138 (at 3.81 20.11) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.33) (end -1.27 19.11) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 19.11) (end 8.89 19.11) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 19.11) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.39) (end -1.33 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 19.17) (end 8.95 19.17) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 19.17) (end 8.95 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.55 -1.6) (end -1.55 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.55 19.4) (end 9.15 19.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 19.4) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 5 A12))
(pad 9 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 A13))
(pad 10 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 A14))
(pad 11 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 "Net-(J2-Pad9)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(J2-Pad7)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 33 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 2 A15))
(pad 14 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 32 "Net-(J2-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 15 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 "Net-(J2-Pad1)"))
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 16 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-16_W7.62mm_Socket.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5C06F4B8) (tstamp 5C06E7DD)
(at 107.95 83.185)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C045943)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U8 (at 3.81 7.62) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74HCT04 (at 3.81 17.57) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 76 "Net-(U8-Pad2)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 77 ~VDU_WRITE))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 78 "Net-(U8-Pad10)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 79 "Net-(U10-Pad2)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 21 R/~W))
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 80 "Net-(U8-Pad5)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 81 "Net-(U10-Pad1)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 82 "Net-(U8-Pad6)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 83 ~VDU_CTRL))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5C06F4BB) (tstamp 5C06E7EF)
(at 123.19 83.185)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C0B0DF2)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U9 (at 3.81 7.62) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74HCT00 (at 3.81 17.57) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 A10))
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 A11))
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 80 "Net-(U8-Pad5)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 80 "Net-(U8-Pad5)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 76 "Net-(U8-Pad2)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 76 "Net-(U8-Pad2)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 77 ~VDU_WRITE))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 82 "Net-(U8-Pad6)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 PHI2))
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 83 ~VDU_CTRL))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 78 "Net-(U8-Pad10)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Housings_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 5C06F4BD) (tstamp 5C06E801)
(at 138.43 83.185)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5C0B1035)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference U10 (at 3.81 7.62) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74HCT00 (at 3.81 17.57) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 16.8) (end 8.7 16.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 16.8) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 7.62) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 81 "Net-(U10-Pad1)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 8 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 84 "Net-(U10-Pad12)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 79 "Net-(U10-Pad2)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 9 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 75 ~CS_CTRL_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 10 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 74 ~CS_RAM_EXT))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 77 ~VDU_WRITE))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 11 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 73 RAM_RW))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 77 ~VDU_WRITE))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 12 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 84 "Net-(U10-Pad12)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 85 "Net-(U10-Pad13)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 13 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 85 "Net-(U10-Pad13)"))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(pad 14 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-14_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Oscillators:Oscillator_DIP-14 (layer F.Cu) (tedit 5C06EE63) (tstamp 5C06E809)
(at 100.33 50.165 180)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(descr "Oscillator, DIP14, http://cdn-reichelt.de/documents/datenblatt/B400/OSZI.pdf")
(tags oscillator)
(path /5C04593A)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text reference X1 (at 7.62 -3.81 180) (layer F.SilkS)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text value "3.579545 MHz" (at 7.62 0 180) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(fp_text user %R (at 7.62 -3.81 180) (layer F.Fab)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 18.22 2.79) (end 18.22 -10.41) (layer F.CrtYd) (width 0.05))
(fp_line (start 18.22 -10.41) (end -2.98 -10.41) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.98 -10.41) (end -2.98 2.79) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.98 2.79) (end 18.22 2.79) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.97 1.19) (end 16.97 -8.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.38 -9.16) (end 16.62 -9.16) (layer F.Fab) (width 0.1))
(fp_line (start -1.73 1.54) (end -1.73 -8.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.73 1.54) (end 16.62 1.54) (layer F.Fab) (width 0.1))
(fp_line (start -2.83 -9.51) (end -2.83 2.64) (layer F.SilkS) (width 0.12))
(fp_line (start 17.32 -10.26) (end -2.08 -10.26) (layer F.SilkS) (width 0.12))
(fp_line (start 18.07 1.89) (end 18.07 -9.51) (layer F.SilkS) (width 0.12))
(fp_line (start -2.83 2.64) (end 17.32 2.64) (layer F.SilkS) (width 0.12))
(fp_line (start -2.73 2.54) (end 17.32 2.54) (layer F.Fab) (width 0.1))
(fp_line (start 17.97 -9.51) (end 17.97 1.89) (layer F.Fab) (width 0.1))
(fp_line (start -2.08 -10.16) (end 17.32 -10.16) (layer F.Fab) (width 0.1))
(fp_line (start -2.73 2.54) (end -2.73 -9.51) (layer F.Fab) (width 0.1))
(fp_arc (start 16.62 1.19) (end 16.97 1.19) (angle 90) (layer F.Fab) (width 0.1))
(fp_arc (start 16.62 -8.81) (end 16.62 -9.16) (angle 90) (layer F.Fab) (width 0.1))
(fp_arc (start -1.38 -8.81) (end -1.73 -8.81) (angle 90) (layer F.Fab) (width 0.1))
(fp_arc (start 17.32 1.89) (end 18.07 1.89) (angle 90) (layer F.SilkS) (width 0.12))
(fp_arc (start 17.32 -9.51) (end 17.32 -10.26) (angle 90) (layer F.SilkS) (width 0.12))
(fp_arc (start -2.08 -9.51) (end -2.83 -9.51) (angle 90) (layer F.SilkS) (width 0.12))
(fp_arc (start 17.32 1.89) (end 17.97 1.89) (angle 90) (layer F.Fab) (width 0.1))
(fp_arc (start 17.32 -9.51) (end 17.32 -10.16) (angle 90) (layer F.Fab) (width 0.1))
(fp_arc (start -2.08 -9.51) (end -2.73 -9.51) (angle 90) (layer F.Fab) (width 0.1))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 0 -7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 1 VCC))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 8 thru_hole circle (at 15.24 -7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(net 40 VDU_CLK))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(pad 7 thru_hole circle (at 15.24 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 GND))
Forced KiCad to actually use GND as ground name
2018-12-04 20:47:30 +00:00
(model ${KISYS3DMOD}/Oscillators.3dshapes/Oscillator_DIP-14.wrl
(at (xyz 0 0 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 0 0 0))
)
Fixed footprint error
2018-12-04 20:36:13 +00:00
)
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(module Pin_Headers:Pin_Header_Straight_2x05_Pitch2.54mm (layer F.Cu) (tedit 5C06F481) (tstamp 5C06E9A6)
(at 145.415 118.745)
(descr "Through hole straight pin header, 2x05, 2.54mm pitch, double rows")
(tags "Through hole pin header THT 2x05 2.54mm double row")
(path /5C0413AA)
(fp_text reference J2 (at 1.27 -2.54) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VDU_BASE (at 1.27 12.49) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 -1.27) (end 3.81 11.43) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 11.43) (end -1.27 11.43) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 11.43) (end -1.27 0) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 11.49) (end 3.87 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start 3.87 -1.33) (end 3.87 11.49) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 11.95) (end 4.35 11.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.35 11.95) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 1.27 -2.54 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 "Net-(J2-Pad1)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(pad 3 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 32 "Net-(J2-Pad3)"))
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(pad 5 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 33 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 2.54 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(pad 7 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 34 "Net-(J2-Pad7)"))
(pad 8 thru_hole oval (at 2.54 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(pad 9 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 35 "Net-(J2-Pad9)"))
(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 VDU_BASE))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_2x05_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x07_Pitch2.54mm (layer F.Cu) (tedit 5C06F5C4) (tstamp 5C06F7C4)
(at 121.92 48.26 90)
(descr "Through hole straight pin header, 1x07, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x07 2.54mm single row")
(path /5C0D33B4)
(fp_text reference J3 (at 0 -2.54 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VIDEO (at 2.54 7.62 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 16.51) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 16.51) (end -1.27 16.51) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 16.51) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 16.57) (end 1.33 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 17.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 17.05) (end 1.8 17.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 17.05) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.54 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J3-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(J3-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 38 "Net-(J3-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 39 Y))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 40 VDU_CLK))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 86 GND))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 VCC))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x07_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module vdu_amplifier:Amplifier (layer F.Cu) (tedit 5C128446) (tstamp 5C12772C)
(at 134.62 75.565)
(path /5C12C79F)
(fp_text reference U11 (at 0 1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VDU_Port (at 0 -1.905) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 16.51 -10.16) (end 16.51 -12.065) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 -12.065) (end -20.32 -12.065) (layer F.SilkS) (width 0.15))
(fp_line (start -20.32 -12.065) (end -20.32 -10.16) (layer F.SilkS) (width 0.15))
(fp_line (start -16.51 5.715) (end -20.32 5.715) (layer F.SilkS) (width 0.15))
(fp_line (start -20.32 5.715) (end -20.32 -10.16) (layer F.SilkS) (width 0.15))
(fp_line (start -14.605 1.27) (end -10.795 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -10.795 -1.27) (end -14.605 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -16.51 5.715) (end 16.51 5.715) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 5.715) (end 16.51 5.08) (layer F.SilkS) (width 0.15))
(fp_line (start 16.51 5.08) (end 16.51 -10.16) (layer F.SilkS) (width 0.15))
(fp_line (start -10.795 1.27) (end -10.16 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -10.16 -1.27) (end -10.795 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -10.16 1.27) (end -7.62 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -7.62 3.81) (end 0 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -10.16 -1.27) (end -7.62 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start -7.62 -3.81) (end 0 -3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 3.81) (end 9.525 4.445) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 3.81) (end 9.525 3.175) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 -3.81) (end 9.525 -3.175) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 -3.81) (end 9.525 -4.445) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 3.81) (end 8.89 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 0 3.81) (end 10.16 3.81) (layer F.SilkS) (width 0.15))
(fp_line (start 10.16 -3.81) (end 0 -3.81) (layer F.SilkS) (width 0.15))
(fp_text user GND (at 12.7 -1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user GND (at 12.7 1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user AUD (at 12.7 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user VID (at 12.7 -3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user AUD (at -16.51 1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user VID (at -16.51 -1.27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user GND (at -16.51 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user VCC (at -16.51 -3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at -19.05 -3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 1 VCC))
(pad 2 thru_hole circle (at -19.05 -1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 39 Y))
(pad 4 thru_hole circle (at -19.05 1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at -19.05 3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 15.24 -3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 41 "Net-(J8-Pad2)"))
(pad 6 thru_hole circle (at 15.24 -1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at 15.24 1.27) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at 15.24 3.81) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask))
)
Fixed footprint error
2018-12-04 20:36:13 +00:00
(gr_line (start 151.765 144.145) (end 52.705 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 151.765 44.45) (end 52.705 44.45) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 151.765 144.145) (end 151.765 44.45) (angle 90) (layer Edge.Cuts) (width 0.15))
(gr_line (start 52.705 44.45) (end 52.705 144.145) (angle 90) (layer Edge.Cuts) (width 0.15))
Changed VDU CS logic ins schematic
2018-12-29 12:56:20 +00:00
(segment (start 115.57 71.755) (end 119.38 71.755) (width 0.25) (layer B.Cu) (net 1) (status 400000))
(segment (start 120.65 73.025) (end 120.65 80.645) (width 0.25) (layer B.Cu) (net 1) (tstamp 5C1D53A8))
(segment (start 119.38 71.755) (end 120.65 73.025) (width 0.25) (layer B.Cu) (net 1) (tstamp 5C1D539D))
(segment (start 118.745 140.97) (end 111.125 140.97) (width 0.25) (layer B.Cu) (net 1))
(segment (start 151.13 139.7) (end 149.86 140.97) (width 0.25) (layer B.Cu) (net 1) (tstamp 5C06FBB8))
(segment (start 149.86 140.97) (end 118.745 140.97) (width 0.25) (layer B.Cu) (net 1) (tstamp 5C06FBB9))
(segment (start 151.13 107.315) (end 151.13 139.7) (width 0.25) (layer B.Cu) (net 1))
(segment (start 111.125 140.97) (end 109.22 140.97) (width 0.25) (layer F.Cu) (net 1) (tstamp 5C070496))
(via (at 111.125 140.97) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 126.365 108.585) (end 113.665 108.585) (width 0.25) (layer B.Cu) (net 1))
(segment (start 112.395 109.855) (end 112.395 111.125) (width 0.25) (layer B.Cu) (net 1) (tstamp 5C06FB47))
(segment (start 112.395 109.855) (end 113.665 108.585) (width 0.25) (layer B.Cu) (net 1))
(segment (start 109.22 140.97) (end 107.315 142.875) (width 0.25) (layer F.Cu) (net 1) (tstamp 5C06FBCA))
(segment (start 72.39 108.585) (end 73.66 109.855) (width 0.25) (layer B.Cu) (net 1))
(segment (start 73.66 109.855) (end 73.66 111.125) (width 0.25) (layer B.Cu) (net 1))
(segment (start 53.34 107.315) (end 53.34 139.7) (width 0.25) (layer B.Cu) (net 1))
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)
)
Fixed footprint error
2018-12-04 20:36:13 +00:00
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