Merge pull request #12 from 0cjs/dev/cjs/200206/bus
Document RC6502 Bus
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RC6502 Bus
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==========
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The RC6502 system uses a 39-pin bus; the physical layout is a single
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row of 0.05" square header pins on 0.1" centers. Conventionally the
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boards have a male right-angle connector on one edge and these are
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plugged into a [backplane] with female connectors.
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The pinout is as follows. The signal directions (input or output from
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the point of view of CPU and peripheral boards, respectively) are
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guidelines, and a specific board might have a different direction. For
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signals where both are marked `in`, both CPU and peripheral boards are
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usually capable of using the signal as an input, but it's expected
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that one board in the system will be generating the signal.
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Signal Pin CPU Periph
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Name No. Dir. Dir. Notes
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--------------------------------------------------------------
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A15 1 out in
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… …
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A0 16 out in
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GND 17 in in
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Vcc 18 in in
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Φ2out 19 in in
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/RESET 20 in in Must be actively controlled by one board
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Φ0in 21 in in
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/IRQ 22 in in Pull-up req'd; usually provided by CPU board
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Φ1out 23 in in Little used; also called EX0
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R/W̅ 24 out in
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RDY 25 in out
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SYNC 26 out in
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D0 27 ↔ ↔
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… …
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D7 34 ↔ ↔
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TX 35 ? ?
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RX 36 ? ?
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/NMI 37 in out Pull-up req'd; usually provided by CPU board
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× 38 Also known as EX1
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× 39 Also known as EX2
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Signal Use
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----------
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This section gives, for each group of signals:
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- Additional information on how the signal is wired and/or used, where not
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obvious.
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- Which boards take the signal(s) as input and/or output.
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- Any special uses or behaviour by certain boards.
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### GND/Vcc
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Must be supplied by only one board. Only the following boards have
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provision to supply power.
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- [Backplane]: Provision to supply 5 V via an LM7805 regulator or directly
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from the backplane power input if JP1 is shorted.
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- [SBC]: Jumper J8, when closed, supplies 5 V from the Arduino Nano board,
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which in turn is powered by the USB connection. The Nano and the SBC
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board (with NMOS parts) draw 200-250 mA. Depending on what kind of port
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the USB cable is connected to, it will usually provide a maximum of 100
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mA, 500 mA or 1000 mA.
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### D0…D7
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All data lines are used by virtually all boards as both inputs and outputs.
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### A0…A15, R/W̅
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At the moment only CPU boards drive the address and R/W̅ lines. No current
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CPU boards have provision for DMA (this would require a CPU with a bus
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enable function or a buffer to isolate the CPU lines from the bus) so no
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peripherals can ever drive these lines.
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- Ouput: [CPU], [SBC].
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- Input: All others.
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### Φ0in: CPU Clock Source
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Φ0in is normally used only by the CPU (other boards needing the system
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clock use Φ2out).
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- Input:
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- [CPU]: Required input signal, usu. provided by the [Reset] board.
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- [SBC]: Taken from bus if JP1 open.
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- [Debug]: Required input signal.
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- [TIA]: Input to TIA chip.
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- Output:
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- [Reset]: Supplied to bus or not based on jumper block J2 setting.
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- [SBC]: Supplied to bus (and CPU) if JP1 shorted.
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### Φ2out: System Clock
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Φ2out is a CPU output signal and is driven only by CPU boards. It's used as
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an input on many boards, often for qualification of the R/W̅ signal.
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### Φ1out/EX0
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Φ1out is a CPU output signal. The [SBC] board sends it to the bus, but the
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[CPU] board does not. No boards appear to use this. The bus signal is
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marked as EX0 on some schematics.
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### /RESET
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The /RESET line circuits are expected always to drive the /RESET line;
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boards should not provide pullups for it (and no boards are known to do
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so). Thus, only one reset circuit may be on the bus.
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- Output: [Reset], [SBC]. Neither can be disabled, so these two boards are
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incompatible with each other.
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- Input: [CPU], [RIOT], [Serial IO], [Terminal].
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### /IRQ, /NMI
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The interrupt lines are open-collector, with pull-ups usually supplied by
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the CPU board.
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- Pull-ups: [CPU] and [SBC] provide 3.3 kΩ pullups that cannot be disabled.
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- Input:
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- [CPU]: Inputs are enabled with jumpers shorting J2 (IRQ) and J3 (NMI)
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- [SBC]: Inputs are always enabled
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- Output:
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- [RIOT]: 6532 `I̅R̅Q̅` signal (pin 25) to bus if JP1 pins 2/3 shorted. JP7
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pins 1/2 shorted sends to /IRQ, pins 2/3 shorted sends to /NMI.
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- [VDU]: MC6847 `F̅S̅` signal (pin 37) to bus /IRQ if JP3 shorted.
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### RDY
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/RDY is a CPU input signal; the [CPU] and [SBC] boards provide a 3.3 kΩ
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pullup on this line.
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The following boards generate RDY output:
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- [Debug]
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- [TIA]
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### SYNC
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SYNC is a CPU output, and is generated only by the [CPU] and [SBC] boards.
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Input:
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- [Debug]: Used as an input to the single-step circuit.
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### TX, RX
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- [SBC]: Connected to the Arduino Nano; TX is the D1/TX output and RX is
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the D0/RX input.
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- [Serial IO]: Connected to the Arduino Nano; TX is the D1/TX output and RX
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is the D0/RX input.
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### Pin 38 (EX1)
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The following boards may optionally use this line as an input:
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- [TIA]: If JP5 (T0_EN) is shorted, use this as the T0/I4 (pin 36) input
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for the TIA chip. This is a latched input port typically used for
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joystick/paddle triggers.
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The following boards may optionally use this line as an output:
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- [RIOT]: If JP5 (T0_EN) is shorted, connect the right player
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joystick/paddle fire button signal.
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### Pin 39 (EX2)
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The following boards may optionally use this line as an input:
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- [ROM]: If JP4 is shorted, use this as a "page" input to disable the ROM
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(presumably other boards could use the inversion of this signal to enable
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something else in its place). However, use of this feature is
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discouraged, and many systems may instead use a [RAM] board for ROM as
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well.
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- [TIA]: If JP4 (T1_EN) is shorted, use this as the T1/I5 (pin 35) input
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for the TIA chip. This is a latched input port typically used for
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joystick/paddle triggers.
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The following boards may optionally use this line as an output:
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- [RIOT]: If JP4 (T1_EN) is shorted, connect the left player
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joystick/paddle fire button signal.
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<!-------------------------------------------------------------------->
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[Backplane]: ./RC6502%20Backplane/
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[CPU]: ./RC6502%20CPU/
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[Reset]: ./RC6502%20Reset%20Circuit/
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[SBC]: RC6502%20Apple%201%20SBC/
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[Debug]: ./RC6502%20Debug/
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[RIOT]: ./RC6502%20RIOT/
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[ROM]: ./RC6502%20ROM/
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[Serial IO]: ./RC6502%20Serial%20IO/
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[TIA]: ./RC6502%20TIA%20NTSC/
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[Terminal]: ./RC6502%20Terminal/
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[VDU]: ./RC6502%20VDU/
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@ -14,6 +14,8 @@ I've been documenting the build process of the various components on my blog at
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## Modules
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Like the RC2014 I've decided to keep things very modular with each card more or less doing one simple thing, easier to wrap ones head around as a beginner and a lot easier to understand when troubleshooting - also a lot cheaper to upgrade or replace since you don't actually need to replace the entire thing, just the specific board. With the conversion of the RC6502 computer to a SBC-version (Single Board Computer), you now have the option to build an all in one version on a single PCB - alternatively you can build the completely full-sized version as before if you want to! Most can be accomplished with the SBC version so to start things off, I recommend getting PCBs of the SBC ([order](https://www.pcbway.com/project/shareproject/RC6502_Apple_1_SBC__revision_D_.html?inviteid=88707)) as well as the backplane ([order](https://www.pcbway.com/project/shareproject/RC6502_Apple_1_Replica__Backplane_module_revision_A_.html?inviteid=88707)).
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The full-sized system uses a 39-pin bus described in [`Bus.md`](Bus.md). The SBC supports the same bus, allowing you to use expansion cards with it; jumpers on the SBC allow you to disable any of the RAM, ROM, PIA and clock so that their functionality can be replaced by peripheral cards on the bus.
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In order to build a single board computer (SBC) of RC6502 you'll need the following modules:
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- [RC6502 SBC](https://github.com/tebl/RC6502/tree/master/RC6502%20Apple%201%20SBC) ([order](https://www.pcbway.com/project/shareproject/RC6502_Apple_1_SBC__revision_D_.html?inviteid=88707))
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