Apple-1-HW/RC6502-Apple-1-Replica
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Connected RDY to the wrong pin. Ooops!

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This commit is contained in:
Unknown 2017-06-15 13:35:40 +02:00
parent ec896b5c34
commit 3c2267d4a0
16 changed files with 335 additions and 350 deletions
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324
RC6502 CPU/RC6502 CPU.kicad_pcb
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@ -9,7 +9,7 @@
(tracks 326)
(zones 0)
(modules 12)
(nets 41)
(nets 40)
)
(page A4)
@ -125,13 +125,12 @@
(net 31 NMI)
(net 32 "Net-(J2-Pad1)")
(net 33 "Net-(J3-Pad2)")
(net 34 "Net-(R1-Pad1)")
(net 35 "Net-(JP2-Pad2)")
(net 36 RW)
(net 37 RDY)
(net 38 SYNC)
(net 39 "Net-(J4-Pad2)")
(net 40 "Net-(JP1-Pad2)")
(net 34 "Net-(JP2-Pad2)")
(net 35 RW)
(net 36 RDY)
(net 37 SYNC)
(net 38 "Net-(J4-Pad2)")
(net 39 "Net-(JP1-Pad2)")
(net_class Default "This is the default net class."
(clearance 0.2)
@ -173,7 +172,6 @@
(add_net "Net-(J4-Pad2)")
(add_net "Net-(JP1-Pad2)")
(add_net "Net-(JP2-Pad2)")
(add_net "Net-(R1-Pad1)")
(add_net PHI2)
(add_net RDY)
(add_net RESET)
@ -956,11 +954,11 @@
(net 22 IRQ))
(pad 23 thru_hole oval (at 0 55.88 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(pad 24 thru_hole oval (at 0 58.42 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 RW))
(net 35 RW))
(pad 25 thru_hole oval (at 0 60.96 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 37 RDY))
(net 36 RDY))
(pad 26 thru_hole oval (at 0 63.5 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 38 SYNC))
(net 37 SYNC))
(pad 27 thru_hole oval (at 0 66.04 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 D0))
(pad 28 thru_hole oval (at 0 68.58 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
@ -1164,7 +1162,7 @@
(fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole circle (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(R1-Pad1)"))
(net 36 RDY))
(pad 2 thru_hole oval (at 10.16 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 18 VCC))
(model Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl
@ -1288,15 +1286,14 @@
(fp_line (start 16.9 -1.7) (end -1.7 -1.7) (layer F.CrtYd) (width 0.05))
(fp_arc (start 7.62 -1.39) (end 6.62 -1.39) (angle -180) (layer F.SilkS) (width 0.12))
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 39 "Net-(J4-Pad2)"))
(net 38 "Net-(J4-Pad2)"))
(pad 21 thru_hole oval (at 15.24 48.26 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 GND))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 34 "Net-(R1-Pad1)"))
(net 36 RDY))
(pad 22 thru_hole oval (at 15.24 45.72 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 4 A12))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 37 RDY))
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 23 thru_hole oval (at 15.24 43.18 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 3 A13))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
@ -1311,7 +1308,7 @@
(pad 26 thru_hole oval (at 15.24 35.56 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 30 D7))
(pad 7 thru_hole oval (at 0 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 38 SYNC))
(net 37 SYNC))
(pad 27 thru_hole oval (at 15.24 33.02 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 29 D6))
(pad 8 thru_hole oval (at 0 17.78 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
@ -1341,7 +1338,7 @@
(pad 14 thru_hole oval (at 0 33.02 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 A5))
(pad 34 thru_hole oval (at 15.24 15.24 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 36 RW))
(net 35 RW))
(pad 15 thru_hole oval (at 0 35.56 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 A6))
(pad 35 thru_hole oval (at 15.24 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
@ -1472,7 +1469,7 @@
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 VCC))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 40 "Net-(JP1-Pad2)"))
(net 39 "Net-(JP1-Pad2)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x02_Pitch2.54mm.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
@ -1545,7 +1542,7 @@
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 CLOCK))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 35 "Net-(JP2-Pad2)"))
(net 34 "Net-(JP2-Pad2)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x02_Pitch2.54mm.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
@ -1594,9 +1591,9 @@
(fp_arc (start -2.08 -9.51) (end -2.73 -9.51) (angle 90) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 0 -7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 40 "Net-(JP1-Pad2)"))
(net 39 "Net-(JP1-Pad2)"))
(pad 8 thru_hole circle (at 15.24 -7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 35 "Net-(JP2-Pad2)"))
(net 34 "Net-(JP2-Pad2)"))
(pad 7 thru_hole circle (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 GND))
(model ${KISYS3DMOD}/Oscillators.3dshapes/Oscillator_DIP-14.wrl
@ -1671,7 +1668,7 @@
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 GND))
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 39 "Net-(J4-Pad2)"))
(net 38 "Net-(J4-Pad2)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x02_Pitch2.54mm.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
@ -1769,7 +1766,7 @@
(gr_line (start 100.33 128.27) (end 100.33 140.97) (angle 90) (layer F.SilkS) (width 0.2))
(gr_line (start 97.79 128.27) (end 100.33 128.27) (angle 90) (layer F.SilkS) (width 0.2))
(gr_line (start 97.79 140.97) (end 97.79 128.27) (angle 90) (layer F.SilkS) (width 0.2))
(gr_text "RC6502 CPU\nRevision B" (at 102.235 116.84) (layer F.SilkS)
(gr_text "RC6502 CPU\nRevision C" (at 102.235 116.84) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
)
(gr_line (start 191.77 140.97) (end 92.71 140.97) (angle 90) (layer Edge.Cuts) (width 0.15))
@ -2035,71 +2032,71 @@
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)

224
RC6502 CPU/RC6502 CPU.net
View File

@ -1,7 +1,7 @@
(export (version D)
(design
(source "D:/ownCloud/Documents/Projects/RC6502/RC6502 CPU/RC6502 CPU.sch")
(date "10/06/2017 00:35:26")
(date "14/06/2017 15:22:08")
(tool "Eeschema 4.0.6")
(sheet (number 1) (name /) (tstamps /)
(title_block
@ -245,160 +245,160 @@
(libraries
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\device.lib"))
(library (logical Oscillators)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\Oscillators.lib"))
(library (logical 65xx)
(uri "D:\\ownCloud\\Documents\\Projects\\RC6502\\RC6502 CPU\\65xx.lib"))
(library (logical conn)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib"))
(library (logical Oscillators)
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\Oscillators.lib")))
(uri "C:\\Program Files\\KiCad\\share\\kicad\\library\\conn.lib")))
(nets
(net (code 1) (name "Net-(U1-Pad5)")
(node (ref U1) (pin 5)))
(net (code 2) (name "Net-(U1-Pad35)")
(net (code 1) (name "Net-(U1-Pad35)")
(node (ref U1) (pin 35)))
(net (code 3) (name "Net-(U1-Pad36)")
(net (code 2) (name "Net-(U1-Pad36)")
(node (ref U1) (pin 36)))
(net (code 4) (name "Net-(J4-Pad2)")
(node (ref U1) (pin 1))
(node (ref J4) (pin 2)))
(net (code 5) (name "Net-(X1-Pad1)")
(net (code 3) (name "Net-(U1-Pad5)")
(node (ref U1) (pin 5)))
(net (code 4) (name GND)
(node (ref C1) (pin 2))
(node (ref J4) (pin 1))
(node (ref U1) (pin 21))
(node (ref J1) (pin 17))
(node (ref X1) (pin 7)))
(net (code 5) (name NMI)
(node (ref J1) (pin 37))
(node (ref J3) (pin 1)))
(net (code 6) (name "Net-(X1-Pad1)")
(node (ref X1) (pin 1)))
(net (code 6) (name VCC)
(node (ref JP1) (pin 1))
(node (ref U1) (pin 38))
(node (ref C1) (pin 1))
(node (ref J1) (pin 18))
(node (ref R3) (pin 2))
(node (ref R2) (pin 2))
(node (ref R1) (pin 2))
(node (ref U1) (pin 8)))
(net (code 7) (name "Net-(JP1-Pad2)")
(node (ref X1) (pin 14))
(node (ref JP1) (pin 2)))
(net (code 8) (name "Net-(JP2-Pad2)")
(node (ref X1) (pin 8))
(node (ref JP2) (pin 2)))
(net (code 9) (name GND)
(node (ref J1) (pin 17))
(node (ref J4) (pin 1))
(node (ref U1) (pin 21))
(node (ref C1) (pin 2))
(node (ref X1) (pin 7)))
(node (ref JP2) (pin 2))
(node (ref X1) (pin 8)))
(net (code 9) (name "Net-(J4-Pad2)")
(node (ref J4) (pin 2))
(node (ref U1) (pin 1)))
(net (code 10) (name "Net-(J1-Pad23)")
(node (ref J1) (pin 23)))
(net (code 11) (name "Net-(J1-Pad35)")
(net (code 11) (name "Net-(U1-Pad3)")
(node (ref U1) (pin 3)))
(net (code 12) (name "Net-(J1-Pad35)")
(node (ref J1) (pin 35)))
(net (code 12) (name "Net-(J1-Pad36)")
(net (code 13) (name "Net-(J1-Pad36)")
(node (ref J1) (pin 36)))
(net (code 13) (name "Net-(J1-Pad38)")
(net (code 14) (name "Net-(J1-Pad38)")
(node (ref J1) (pin 38)))
(net (code 14) (name "Net-(J1-Pad39)")
(net (code 15) (name "Net-(J1-Pad39)")
(node (ref J1) (pin 39)))
(net (code 15) (name NMI)
(node (ref J3) (pin 1))
(node (ref J1) (pin 37)))
(net (code 16) (name IRQ)
(node (ref J1) (pin 22))
(node (ref J2) (pin 2)))
(net (code 17) (name A3)
(net (code 16) (name VCC)
(node (ref R1) (pin 2))
(node (ref R3) (pin 2))
(node (ref C1) (pin 1))
(node (ref U1) (pin 38))
(node (ref J1) (pin 18))
(node (ref U1) (pin 8))
(node (ref R2) (pin 2))
(node (ref JP1) (pin 1)))
(net (code 17) (name IRQ)
(node (ref J2) (pin 2))
(node (ref J1) (pin 22)))
(net (code 18) (name A3)
(node (ref J1) (pin 13))
(node (ref U1) (pin 12)))
(net (code 18) (name A2)
(net (code 19) (name A2)
(node (ref J1) (pin 14))
(node (ref U1) (pin 11)))
(net (code 19) (name A1)
(node (ref J1) (pin 15))
(node (ref U1) (pin 10)))
(net (code 20) (name RDY)
(node (ref U1) (pin 3))
(node (ref J1) (pin 25)))
(net (code 21) (name A0)
(node (ref J1) (pin 16))
(node (ref U1) (pin 9)))
(net (code 22) (name SYNC)
(net (code 20) (name RW)
(node (ref J1) (pin 24))
(node (ref U1) (pin 34)))
(net (code 21) (name A1)
(node (ref U1) (pin 10))
(node (ref J1) (pin 15)))
(net (code 22) (name RDY)
(node (ref J1) (pin 25))
(node (ref U1) (pin 2))
(node (ref R1) (pin 1)))
(net (code 23) (name A0)
(node (ref U1) (pin 9))
(node (ref J1) (pin 16)))
(net (code 24) (name SYNC)
(node (ref U1) (pin 7))
(node (ref J1) (pin 26)))
(net (code 23) (name A4)
(node (ref J1) (pin 12))
(node (ref U1) (pin 13)))
(net (code 24) (name D0)
(node (ref U1) (pin 33))
(node (ref J1) (pin 27)))
(net (code 25) (name D1)
(net (code 25) (name A4)
(node (ref U1) (pin 13))
(node (ref J1) (pin 12)))
(net (code 26) (name D0)
(node (ref J1) (pin 27))
(node (ref U1) (pin 33)))
(net (code 27) (name D1)
(node (ref U1) (pin 32))
(node (ref J1) (pin 28)))
(net (code 26) (name PHI2)
(node (ref J1) (pin 19))
(node (ref U1) (pin 39)))
(net (code 27) (name D2)
(net (code 28) (name PHI2)
(node (ref U1) (pin 39))
(node (ref J1) (pin 19)))
(net (code 29) (name D2)
(node (ref U1) (pin 31))
(node (ref J1) (pin 29)))
(net (code 28) (name "Net-(R1-Pad1)")
(node (ref R1) (pin 1))
(node (ref U1) (pin 2)))
(net (code 29) (name "Net-(J2-Pad1)")
(node (ref R2) (pin 1))
(node (ref U1) (pin 4))
(node (ref J2) (pin 1)))
(net (code 30) (name "Net-(J3-Pad2)")
(node (ref U1) (pin 6))
(node (ref R3) (pin 1))
(node (ref J3) (pin 2)))
(net (code 31) (name A11)
(node (ref J1) (pin 5))
(node (ref U1) (pin 20)))
(node (ref J3) (pin 2))
(node (ref U1) (pin 6)))
(net (code 31) (name "Net-(J2-Pad1)")
(node (ref U1) (pin 4))
(node (ref J2) (pin 1))
(node (ref R2) (pin 1)))
(net (code 32) (name A10)
(node (ref U1) (pin 19))
(node (ref J1) (pin 6)))
(net (code 33) (name A9)
(node (ref U1) (pin 18))
(node (ref J1) (pin 7)))
(node (ref J1) (pin 7))
(node (ref U1) (pin 18)))
(net (code 34) (name A8)
(node (ref U1) (pin 17))
(node (ref J1) (pin 8)))
(node (ref J1) (pin 8))
(node (ref U1) (pin 17)))
(net (code 35) (name A7)
(node (ref U1) (pin 16))
(node (ref J1) (pin 9)))
(net (code 36) (name A6)
(node (ref J1) (pin 10))
(node (ref U1) (pin 15)))
(net (code 37) (name A5)
(node (ref J1) (pin 11))
(node (ref U1) (pin 14)))
(net (code 38) (name D6)
(node (ref J1) (pin 33))
(node (ref U1) (pin 27)))
(net (code 39) (name CLOCK)
(node (ref J1) (pin 21))
(node (ref JP2) (pin 1))
(node (ref U1) (pin 37)))
(net (code 40) (name D5)
(node (ref U1) (pin 28))
(node (ref J1) (pin 32)))
(net (code 41) (name D4)
(node (ref U1) (pin 15))
(node (ref J1) (pin 10)))
(net (code 37) (name D3)
(node (ref J1) (pin 30))
(node (ref U1) (pin 30)))
(net (code 38) (name A5)
(node (ref U1) (pin 14))
(node (ref J1) (pin 11)))
(net (code 39) (name D4)
(node (ref U1) (pin 29))
(node (ref J1) (pin 31)))
(net (code 42) (name D7)
(node (ref U1) (pin 26))
(node (ref J1) (pin 34)))
(net (code 43) (name D3)
(node (ref U1) (pin 30))
(node (ref J1) (pin 30)))
(net (code 44) (name RESET)
(node (ref U1) (pin 40))
(node (ref J1) (pin 20)))
(net (code 45) (name A12)
(net (code 40) (name D6)
(node (ref J1) (pin 33))
(node (ref U1) (pin 27)))
(net (code 41) (name CLOCK)
(node (ref JP2) (pin 1))
(node (ref J1) (pin 21))
(node (ref U1) (pin 37)))
(net (code 42) (name D5)
(node (ref J1) (pin 32))
(node (ref U1) (pin 28)))
(net (code 43) (name A12)
(node (ref U1) (pin 22))
(node (ref J1) (pin 4)))
(net (code 44) (name A11)
(node (ref J1) (pin 5))
(node (ref U1) (pin 20)))
(net (code 45) (name RESET)
(node (ref J1) (pin 20))
(node (ref U1) (pin 40)))
(net (code 46) (name A13)
(node (ref J1) (pin 3))
(node (ref U1) (pin 23)))
(node (ref U1) (pin 23))
(node (ref J1) (pin 3)))
(net (code 47) (name A14)
(node (ref U1) (pin 24))
(node (ref J1) (pin 2)))
(net (code 48) (name RW)
(node (ref J1) (pin 24))
(node (ref U1) (pin 34)))
(net (code 49) (name A15)
(node (ref J1) (pin 1))
(node (ref U1) (pin 25)))))
(net (code 48) (name A15)
(node (ref U1) (pin 25))
(node (ref J1) (pin 1)))
(net (code 49) (name D7)
(node (ref J1) (pin 34))
(node (ref U1) (pin 26)))))

4
RC6502 CPU/RC6502 CPU.pro
View File

@ -1,4 +1,4 @@
update=10/06/2017 01:39:04
update=14/06/2017 15:23:44
version=1
last_client=kicad
[pcbnew]
@ -67,7 +67,7 @@ PageLayoutDescrFile=
PlotDirectoryName=D:/ownCloud/Documents/Projects/RC6502/RC6502 CPU/export/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60

6
RC6502 CPU/RC6502 CPU.sch
View File

@ -392,8 +392,12 @@ Text GLabel 9350 3900 0 60 Input ~ 0
RDY
Text GLabel 9350 4000 0 60 Input ~ 0
SYNC
Text GLabel 2000 1800 0 60 Output ~ 0
Text GLabel 1600 2375 3 60 Output ~ 0
RDY
Text GLabel 2000 2200 0 60 Output ~ 0
SYNC
Wire Wire Line
1600 2375 1600 1700
Connection ~ 1600 1700
NoConn ~ 2000 1800
$EndSCHEMATC

48
RC6502 CPU/export/RC6502 CPU-B.Cu.gbl
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Copper,L2,Bot,Signal*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 01:38:28*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/14/17 15:23:26*
%MOMM*%
%LPD*%
G01*
@ -160,10 +160,10 @@ X125095000Y-99060000D03*
X111125000Y-111125000D03*
X125730000Y-111125000D03*
X131445000Y-111125000D03*
X129540000Y-135255000D03*
X111125000Y-113030000D03*
X125095000Y-113030000D03*
X131445000Y-113030000D03*
X129540000Y-135255000D03*
X128905000Y-136525000D03*
X145415000Y-100965000D03*
X137795000Y-117475000D03*
@ -218,6 +218,18 @@ X136525000Y-113030000D02*
X134620000Y-111125000D01*
X144780000Y-119380000D02*
X144780000Y-124460000D01*
X130810000Y-127000000D02*
X133350000Y-127000000D01*
X129540000Y-135255000D02*
X129540000Y-128905000D01*
X129540000Y-128905000D02*
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X129540000Y-128270000D02*
X130810000Y-127000000D01*
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X134620000Y-124460000D01*
X133350000Y-127000000D02*
X134620000Y-125730000D01*
X133985000Y-113030000D02*
X131445000Y-113030000D01*
X134620000Y-113665000D02*
@ -226,18 +238,6 @@ X134620000Y-113665000D02*
X134620000Y-124460000D01*
X125095000Y-113030000D02*
X111125000Y-113030000D01*
X137160000Y-125730000D02*
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X128905000Y-136525000D01*
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@ -1363,14 +1363,8 @@ X133331441Y-125724090D01*
X133476431Y-125511890D01*
X133507815Y-125356911D01*
X133605302Y-125502811D01*
X134070849Y-125813880D01*
X134620000Y-125923113D01*
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X135890000Y-125120725D01*
X136145302Y-125502811D01*
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X133035198Y-126240000D01*
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X130272599Y-126462599D01*
@ -2828,14 +2822,8 @@ X133331441Y-125724090D01*
X133476431Y-125511890D01*
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X133605302Y-125502811D01*
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X130810000Y-126240000D01*
X130519160Y-126297852D01*
X130272599Y-126462599D01*

2
RC6502 CPU/export/RC6502 CPU-B.Mask.gbs
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Soldermask,Bot*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 01:38:28*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/14/17 15:23:26*
%MOMM*%
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2
RC6502 CPU/export/RC6502 CPU-B.Paste.gbp
View File

@ -1,7 +1,7 @@
G04 #@! TF.FileFunction,Paste,Bot*
%FSLAX46Y46*%
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G04 Created by KiCad (PCBNEW 4.0.6) date 06/10/17 01:38:28*
G04 Created by KiCad (PCBNEW 4.0.6) date 06/14/17 15:23:26*
%MOMM*%
%LPD*%
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2
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RC6502 CPU/export/RC6502 CPU.pdf
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