12 Commits

Author	SHA1	Message	Date
Unknown	8ad4584e91	Added RAM README	2019-01-14 22:25:28 +01:00
Unknown	d0f6b369fd	Changed VDU CS logic ins schematic	2018-12-29 13:56:20 +01:00
Unknown	f36f8700e3	Flipped decoder inputs, added details to silkscreen.	2018-12-23 01:12:14 +01:00
Unknown	6fd7df5eb0	Enhanced RAM/ROM board, routing done	2018-12-22 17:09:04 +01:00
Unknown	7dbb3f715b	Schematic done for enhanced RAM/ROM board	2018-12-21 19:00:00 +01:00
Unknown	e51a21e59a	RAM revision B ... Fixed silkscreen notes by swapping high/low text, moved around tracks to make it a little more compact.	2017-06-10 17:50:00 +02:00
Unknown	12f925f831	Added pictures of working setup	2017-06-02 20:24:48 +02:00
Unknown	814df351cb	Renamed some pins	2017-06-01 19:41:30 +02:00
Unknown	789a7bdd18	Exported all schematics to PDF	2017-05-31 01:10:27 +02:00
Unknown	5bcb7ba543	Exported files	2017-05-15 22:54:58 +02:00
Unknown	4197312ab0	Updated net lists	2017-05-14 21:51:11 +02:00
Unknown	ef9b1b5ff8	Added files	2017-05-14 21:08:06 +02:00