apple1serial/mapping/address_decoder-C300.log

EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
Copyright (c) National Semiconductor Corporation 1990-1993

Log file for ADDRES~1.EQN
Device: 20V8

Pin   Label               Type
---   -----               ----
2     RW                  pos,com input
3     A8                  pos,com input
4     A7                  pos,com input
5     A6                  pos,com input
6     A5                  pos,com input
7     A4                  pos,com input
8     A3                  pos,com input
9     A2                  pos,com input
10    A1                  pos,com input
11    A0                  pos,com input
12    GND                 ground pin
14    A11                 pos,com input
15    A10                 pos,com input
16    A9                  pos,com input
17    SR                  pos,com output
18    RD                  pos,com output
19    WD                  pos,com output
20    ROM                 neg,com output
21    RES                 pos,com output
22    PHI                 pos,com input
23    T                   pos,com input
24    VCC                 power pin

EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
Copyright (c) National Semiconductor Corporation 1990-1993

Device Utilization:

No of dedicated inputs used               : 14/14 (100.0%)
No of feedbacks used as dedicated inputs  :  1/6  (16.7%)
No of dedicated outputs used              :  2/2  (100.0%)
No of feedbacks used as dedicated outputs :  3/6  (50.0%)

		------------------------------------------
		Pin   Label                 Terms Usage
		------------------------------------------
		21    RES                   1/8   (12.5%)
		20    ROM                   3/8   (37.5%)
		19    WD                    1/8   (12.5%)
		18    RD                    1/8   (12.5%)
		17    SR                    1/8   (12.5%)
		------------------------------------------
		Total Terms                 7/64  (10.9%)
		------------------------------------------

EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
Copyright (c) National Semiconductor Corporation 1990-1993

                            Chip diagram (DIP)

                             ._____    _____.
                             |     \__/     |
                             |  1        24 | VCC
                          RW |  2        23 | T
                          A8 |  3        22 | PHI
                          A7 |  4        21 | RES
                          A6 |  5        20 | ROM
                          A5 |  6        19 | WD
                          A4 |  7        18 | RD
                          A3 |  8        17 | SR
                          A2 |  9        16 | A9
                          A1 | 10        15 | A10
                          A0 | 11        14 | A11
                         GND | 12        13 | 
                             |______________|