mirror of https://github.com/datajerk/espple.git
Initial commit.
This commit is contained in:
Hrvoje Čavrak
commit
53173fcebe
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|
@ -0,0 +1,3 @@
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|||
image.elf
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||||
image.lst
|
||||
image.map
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
The MIT License (MIT)
|
||||
|
||||
Copyright (c) 2016 CNLohr
|
||||
2017 Hrvoje Cavrak
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
# ---------- CONFIG SECTION ---------- #
|
||||
|
||||
PORT:=/dev/ttyUSB0
|
||||
BITRATE:=115200
|
||||
MODE:=dio
|
||||
|
||||
GCC_FOLDER:=/opt/esp8266/esp-open-sdk/xtensa-lx106-elf
|
||||
ESPTOOL_PY:=/usr/share/esptool/esptool.py
|
||||
SDK:=/opt/esp8266/esp_iot_sdk_v1.3.0/
|
||||
|
||||
# ------------------------------------ #
|
||||
|
||||
FW_FILE_1:=image.elf-0x00000.bin
|
||||
FW_FILE_2:=image.elf-0x40000.bin
|
||||
TARGET_OUT:=image.elf
|
||||
all : $(TARGET_OUT) $(FW_FILE_1) $(FW_FILE_2)
|
||||
|
||||
SRCS:=user/fake6502.c user/generate_video.c user/user_main.c
|
||||
|
||||
XTLIB:=$(SDK)/lib
|
||||
XTGCCLIB:=$(GCC_FOLDER)/lib/gcc/xtensa-lx106-elf/4.8.5/libgcc.a
|
||||
FOLDERPREFIX:=$(GCC_FOLDER)/bin
|
||||
CC:=$(FOLDERPREFIX)/$(PREFIX)gcc
|
||||
PREFIX:=$(FOLDERPREFIX)/xtensa-lx106-elf-
|
||||
|
||||
CFLAGS:=-mlongcalls -I$(SDK)/include -Iinclude -O3 -I$(SDK)/include/ -DICACHE_FLASH
|
||||
LDFLAGS_CORE:=-nostdlib -Wl,--start-group -lmain -lnet80211 -lcrypto -lssl -lwpa -llwip -lpp -lphy -Wl,--end-group -lgcc -T$(SDK)/ld/eagle.app.v6.ld
|
||||
|
||||
LINKFLAGS:= $(LDFLAGS_CORE) -B$(XTLIB)
|
||||
|
||||
$(TARGET_OUT) : $(SRCS)
|
||||
$(PREFIX)gcc $(CFLAGS) $^ $(LINKFLAGS) -o $@
|
||||
|
||||
$(FW_FILE_1): $(TARGET_OUT)
|
||||
PATH=$(FOLDERPREFIX):$$PATH;$(ESPTOOL_PY) elf2image --flash_mode $(MODE) $(TARGET_OUT)
|
||||
|
||||
$(FW_FILE_2): $(TARGET_OUT)
|
||||
PATH=$(FOLDERPREFIX):$$PATH;$(ESPTOOL_PY) elf2image --flash_mode $(MODE) $(TARGET_OUT)
|
||||
|
||||
flash :
|
||||
$(ESPTOOL_PY) -b $(BITRATE) --port $(PORT) write_flash --flash_mode $(MODE) 0x00000 image.elf-0x00000.bin 0x40000 image.elf-0x40000.bin
|
||||
|
||||
credentials :
|
||||
python -c "open('wifi_credentials.bin', 'wb').write(''.join(i.ljust(32, '\0') for i in ['$(ssid)','$(password)']))"
|
||||
$(ESPTOOL_PY) --port $(PORT) write_flash 0x3c000 wifi_credentials.bin
|
||||
rm wifi_credentials.bin
|
||||
|
||||
clean :
|
||||
rm -rf user/*.o driver/*.o $(TARGET_OUT) $(FW_FILE_1) $(FW_FILE_2)
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
# espple - Apple 1 Emulator with PAL RF Output
|
||||
|
||||
Try out the original Apple 1 with a 3$ ESP8266 board on your living room TV - **wirelessly**!
|
||||
|
||||
|
||||
|
||||
## Features
|
||||
|
||||
- MOS 6502 CPU emulated at native speed (1 MHz)
|
||||
- 20 kB RAM
|
||||
- PAL TV signal output
|
||||
- Original Signetics 2513 ROM characters
|
||||
- Telnet used for keyboard input
|
||||
- Built-in TFTP server for uploading software
|
||||
- Everything is wireless
|
||||
|
||||
## How does it work?
|
||||
|
||||
Video generation is done using the internal I2S bus / DMA functionality.
|
||||
|
||||
I2S stands for Inter-IC Sound, a standard for digital audio devices interconnect. ESP8266 supports I2S bus data output using DMA transfers, providing a way to generate a steady stream of bits while the processor can do something else. It gets interrupted when the 'bucket' is empty, and it fills it again with more bits to be pumped out.
|
||||
|
||||
By generating patterns in those bits, it's possible to produce a meaningful waveform which can be interpreted as a video signal by a TV. Since I live in Europe, the chosen video system is 625 lines CCIR system B (basically PAL B without the color).
|
||||
|
||||
|
||||
|
||||
---
|
||||
|
||||
## Instructions
|
||||
|
||||
### Flashing the files
|
||||
|
||||
1. Install programmer software.
|
||||
* Linux - install [esptool](https://github.com/espressif/esptool) (_apt-get install esptool_ on debian-like systems, _pip install esptool_ or _git clone_ the repo),
|
||||
* Windows - use [Flash download tools](http://espressif.com/en/support/download/other-tools)
|
||||
|
||||
|
||||
2. Write the binary files (adjust your port name)
|
||||
|
||||
```
|
||||
esptool -p /dev/ttyUSB0 write_flash --flash_mode dio 0x00000 image.elf-0x00000.bin 0x40000 image.elf-0x40000.bin
|
||||
```
|
||||
|
||||
Tip - ESP-12E modules require flash_mode dio, most other boards use qio.
|
||||
|
||||
3. Provide your wi-fi credentials
|
||||
|
||||
```
|
||||
make credentials ssid="Your SSID" password="Your password"
|
||||
```
|
||||
|
||||
This will generate a .bin file containing the credentials and write it to flash memory at 0x3FC00. Please keep this in mind and run this command again with dummy credentials if you intend to sell or borrow your ESP board.
|
||||
|
||||
4. Connect a piece of breadboard jumper cable to the RX pin (GPIO 3)
|
||||
|
||||
5. Turn your TV on and select analogue TV, PAL system - channel 4. Some manual fine tuning might be required.
|
||||
|
||||
6. Telnet to the ESP - the IP address can be read through the cable used to flash the firmware. Make sure your terminal program is set to 115200,8N1. Press enter several times after connecting.
|
||||
|
||||
|
||||
### Loading the software
|
||||
|
||||
First you need to tell the built-in TFTP server where to store your program. To keep things simple, this always points to the last memory location examined using the built-in monitor which starts after a reboot (the one with the \ prompt).
|
||||
|
||||
For BASIC, the target address was E000 hex.
|
||||
|
||||
Simply type E000 and press enter, this will specify the upload target address. Then run the TFTP client on your computer and upload the binary file (adjust your target IP accordingly):
|
||||
|
||||
```
|
||||
atftp -l apple-basic.bin 192.168.1.2
|
||||
```
|
||||
|
||||
After TFTP client finishes, simply run the program from target location by typing the location followed by the letter R. If you just transferred BASIC, you would type E000R and be greeted with the '>' prompt.
|
||||
|
||||
### Rebooting
|
||||
|
||||
Press **Ctrl + C** when connected through telnet to trigger emulator reboot. Neither wi-fi or telnet connection will be dropped.
|
||||
|
||||
## Demo
|
||||
|
||||
[](https://www.youtube.com/watch?v=rCqbB1UmW8o)
|
||||
|
||||
Take a look of the Espple in action.
|
||||
|
||||
## Help
|
||||
|
||||
##### Q. Backspace doesn't work - it shows _
|
||||
|
||||
A. This is by design, Apple 1 output works more like a teletype, there is no going back so this is the "rub out" symbol which tells the computer to disregard the previous symbol.
|
||||
|
||||
##### Q. I've flashed your bin files and now I'm in a reboot loop
|
||||
|
||||
A. My board is an ESP-12E, and requires DIO flash mode to be set (2 pins used for address and data) as opposed to QIO mode (4 pins used) some other variants use. Try flashing with QIO and see if that helps.
|
||||
|
||||
##### Q. Wifi doesn't connect
|
||||
|
||||
A. Make sure you've set the credentials like instructed. Try moving the ESP board closer to the access point and configure it to use one of the lower frequency channels (1-6). You can monitor progress using a serial connection (115200, 8N1).
|
||||
|
||||
##### Q. Why can't I simply use the serial as a keyboard input? This wi-fi thing seems overengineered.
|
||||
|
||||
A. Because the UART0 RX line is already being used as an I2S output, and UART1 exposes TX pin only to the board.
|
||||
|
||||
On the plus side, it's totally wireless.
|
||||
|
||||
##### Q. Program doesn't start after TFTP upload
|
||||
|
||||
A. A packet was probably lost, try again and make sure you have a good wi-fi reception.
|
||||
|
||||
##### Q. I can't find a signal on the TV
|
||||
|
||||
A. Your RF input connector and the whole signal path is shielded inside the TV so there should be some sort of antenna plugged in. If you don't have an indoor antenna, a piece of wire will do just fine. Make sure you don't short the tip and ring of your input connector because you won't receive anything. In your TV menu choose analogue TV, choose PAL standard and select channel 4. The esp board emits at 60 MHz which is slightly lower than channel 4 frequency, so you might have to fine tune a bit. Most modern TVs should be able to automatically scan and find the channel for you.
|
||||
|
||||
## Missing features
|
||||
|
||||
The emulator should accomodate for the terminal output delay. It should be possible to upload the original tape audio waveform over tftp and use the original Apple Cassette Interface to read it.
|
||||
|
||||
## License
|
||||
|
||||
This software is licensed under the MIT license.
|
||||
|
||||
## Credits
|
||||
|
||||
Video generation is derived from the much more impressive [channel3](https://github.com/cnlohr/channel3) project by [Charles Lohr](https://github.com/cnlohr).
|
||||
|
||||
CPU core is made using the fake6502 project by Mike Chambers.
|
||||
|
||||
Apple 1 was famously made by Stephen Wozniak, one of the greatest engineers of our time.
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
/* This linker script generated from xt-genldscripts.tpp for LSP . */
|
||||
/* Linker Script for ld -N */
|
||||
MEMORY
|
||||
{
|
||||
dport0_0_seg : org = 0x3FF00000, len = 0x10
|
||||
dram0_0_seg : org = 0x3FFE8000, len = 0x14000
|
||||
iram1_0_seg : org = 0x40100000, len = 0x8000
|
||||
irom0_0_seg : org = 0x40210000, len = 0x5C000
|
||||
}
|
||||
|
||||
PHDRS
|
||||
{
|
||||
dport0_0_phdr PT_LOAD;
|
||||
dram0_0_phdr PT_LOAD;
|
||||
dram0_0_bss_phdr PT_LOAD;
|
||||
iram1_0_phdr PT_LOAD;
|
||||
irom0_0_phdr PT_LOAD;
|
||||
}
|
||||
|
||||
|
||||
/* Default entry point: */
|
||||
ENTRY(call_user_start)
|
||||
EXTERN(_DebugExceptionVector)
|
||||
EXTERN(_DoubleExceptionVector)
|
||||
EXTERN(_KernelExceptionVector)
|
||||
EXTERN(_NMIExceptionVector)
|
||||
EXTERN(_UserExceptionVector)
|
||||
PROVIDE(_memmap_vecbase_reset = 0x40000000);
|
||||
/* Various memory-map dependent cache attribute settings: */
|
||||
_memmap_cacheattr_wb_base = 0x00000110;
|
||||
_memmap_cacheattr_wt_base = 0x00000110;
|
||||
_memmap_cacheattr_bp_base = 0x00000220;
|
||||
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
|
||||
_memmap_cacheattr_wb_trapnull = 0x2222211F;
|
||||
_memmap_cacheattr_wba_trapnull = 0x2222211F;
|
||||
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
|
||||
_memmap_cacheattr_wt_trapnull = 0x2222211F;
|
||||
_memmap_cacheattr_bp_trapnull = 0x2222222F;
|
||||
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
|
||||
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
|
||||
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
|
||||
_memmap_cacheattr_wb_allvalid = 0x22222112;
|
||||
_memmap_cacheattr_wt_allvalid = 0x22222112;
|
||||
_memmap_cacheattr_bp_allvalid = 0x22222222;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.dport0.rodata : ALIGN(4)
|
||||
{
|
||||
_dport0_rodata_start = ABSOLUTE(.);
|
||||
*(.dport0.rodata)
|
||||
*(.dport.rodata)
|
||||
_dport0_rodata_end = ABSOLUTE(.);
|
||||
} >dport0_0_seg :dport0_0_phdr
|
||||
|
||||
.dport0.literal : ALIGN(4)
|
||||
{
|
||||
_dport0_literal_start = ABSOLUTE(.);
|
||||
*(.dport0.literal)
|
||||
*(.dport.literal)
|
||||
_dport0_literal_end = ABSOLUTE(.);
|
||||
} >dport0_0_seg :dport0_0_phdr
|
||||
|
||||
.dport0.data : ALIGN(4)
|
||||
{
|
||||
_dport0_data_start = ABSOLUTE(.);
|
||||
*(.dport0.data)
|
||||
*(.dport.data)
|
||||
_dport0_data_end = ABSOLUTE(.);
|
||||
} >dport0_0_seg :dport0_0_phdr
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
*(.jcr)
|
||||
_data_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg :dram0_0_phdr
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.sdk.version)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
*(.xt_except_table)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
*(.eh_frame)
|
||||
/* C++ constructor and destructor tables, properly ordered: */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* C++ exception handlers table: */
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
} >dram0_0_seg :dram0_0_phdr
|
||||
|
||||
.bss ALIGN(8) (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
_heap_start = ABSOLUTE(.);
|
||||
/* _stack_sentry = ALIGN(0x8); */
|
||||
} >dram0_0_seg :dram0_0_bss_phdr
|
||||
/* __stack = 0x3ffc8000; */
|
||||
|
||||
.irom0.text : ALIGN(4)
|
||||
{
|
||||
_irom0_text_start = ABSOLUTE(.);
|
||||
|
||||
*libat.a:(.literal.* .text.*)
|
||||
*libcrypto.a:(.literal.* .text.*)
|
||||
*libespnow.a:(.literal.* .text.*)
|
||||
*libjson.a:(.literal.* .text.*)
|
||||
*liblwip.a:(.literal.* .text.*)
|
||||
*libmesh.a:(.literal.* .text.*)
|
||||
*libnet80211.a:(.literal.* .text.*)
|
||||
*libsmartconfig.a:(.literal.* .text.*)
|
||||
*libssl.a:(.literal.* .text.*)
|
||||
*libupgrade.a:(.literal.* .text.*)
|
||||
*libwpa.a:(.literal.* .text.*)
|
||||
*libwpa2.a:(.literal.* .text.*)
|
||||
*libwps.a:(.literal.* .text.*)
|
||||
|
||||
*libmbedtls.a:(.literal.* .text.*)
|
||||
|
||||
*libm.a:(.literal .text .literal.* .text.*)
|
||||
|
||||
*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
|
||||
_irom0_text_end = ABSOLUTE(.);
|
||||
} >irom0_0_seg :irom0_0_phdr
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
*(.UserEnter.text)
|
||||
. = ALIGN(16);
|
||||
*(.DebugExceptionVector.text)
|
||||
. = ALIGN(16);
|
||||
*(.NMIExceptionVector.text)
|
||||
. = ALIGN(16);
|
||||
*(.KernelExceptionVector.text)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
. = ALIGN(16);
|
||||
*(.UserExceptionVector.text)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
. = ALIGN(16);
|
||||
*(.DoubleExceptionVector.text)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
. = ALIGN (16);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
*(.init)
|
||||
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
*(.fini.literal)
|
||||
*(.fini)
|
||||
*(.gnu.version)
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >iram1_0_seg :iram1_0_phdr
|
||||
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >iram1_0_seg :iram1_0_phdr
|
||||
}
|
||||
|
||||
/* get ROM code address */
|
||||
INCLUDE "../ld/eagle.rom.addr.v6.ld"
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
After Width: | Height: | Size: 49 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 194 KiB |
|
|
@ -0,0 +1,183 @@
|
|||
#ifndef _DMASTUFF_H
|
||||
#define _DMASTUFF_H
|
||||
|
||||
#ifndef i2c_bbpll
|
||||
#define i2c_bbpll 0x67
|
||||
#define i2c_bbpll_en_audio_clock_out 4
|
||||
#define i2c_bbpll_en_audio_clock_out_msb 7
|
||||
#define i2c_bbpll_en_audio_clock_out_lsb 7
|
||||
#define i2c_bbpll_hostid 4
|
||||
|
||||
#define i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata) rom_i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata)
|
||||
#define i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb) rom_i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb)
|
||||
#define i2c_writeReg_Mask_def(block, reg_add, indata) \
|
||||
i2c_writeReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb, indata)
|
||||
#define i2c_readReg_Mask_def(block, reg_add) \
|
||||
i2c_readReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb)
|
||||
#endif
|
||||
#ifndef ETS_SLC_INUM
|
||||
#define ETS_SLC_INUM 1
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
//From i2s_reg.h
|
||||
#define DR_REG_I2S_BASE (0x60000e00)
|
||||
|
||||
#define I2STXFIFO (DR_REG_I2S_BASE + 0x0000)
|
||||
#define I2SRXFIFO (DR_REG_I2S_BASE + 0x0004)
|
||||
#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
|
||||
#define I2S_BCK_DIV_NUM 0x0000003F
|
||||
#define I2S_BCK_DIV_NUM_S 22
|
||||
#define I2S_CLKM_DIV_NUM 0x0000003F
|
||||
#define I2S_CLKM_DIV_NUM_S 16
|
||||
#define I2S_BITS_MOD 0x0000000F
|
||||
#define I2S_BITS_MOD_S 12
|
||||
#define I2S_RECE_MSB_SHIFT (BIT(11))
|
||||
#define I2S_TRANS_MSB_SHIFT (BIT(10))
|
||||
#define I2S_I2S_RX_START (BIT(9))
|
||||
#define I2S_I2S_TX_START (BIT(8))
|
||||
#define I2S_MSB_RIGHT (BIT(7))
|
||||
#define I2S_RIGHT_FIRST (BIT(6))
|
||||
#define I2S_RECE_SLAVE_MOD (BIT(5))
|
||||
#define I2S_TRANS_SLAVE_MOD (BIT(4))
|
||||
#define I2S_I2S_RX_FIFO_RESET (BIT(3))
|
||||
#define I2S_I2S_TX_FIFO_RESET (BIT(2))
|
||||
#define I2S_I2S_RX_RESET (BIT(1))
|
||||
#define I2S_I2S_TX_RESET (BIT(0))
|
||||
#define I2S_I2S_RESET_MASK 0xf
|
||||
|
||||
#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
|
||||
#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
|
||||
#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
|
||||
#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
|
||||
#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
|
||||
|
||||
|
||||
#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
|
||||
#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
|
||||
#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
|
||||
#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
|
||||
#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
|
||||
|
||||
#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
|
||||
#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
|
||||
#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
|
||||
#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
|
||||
#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
|
||||
#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
|
||||
#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
|
||||
|
||||
#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
|
||||
#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
|
||||
#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
|
||||
#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
|
||||
#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
|
||||
#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
|
||||
#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
|
||||
|
||||
#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
|
||||
#define I2S_TRANS_BCK_IN_INV (BIT(22))
|
||||
#define I2S_RECE_DSYNC_SW (BIT(21))
|
||||
#define I2S_TRANS_DSYNC_SW (BIT(20))
|
||||
#define I2S_RECE_BCK_OUT_DELAY 0x00000003
|
||||
#define I2S_RECE_BCK_OUT_DELAY_S 18
|
||||
#define I2S_RECE_WS_OUT_DELAY 0x00000003
|
||||
#define I2S_RECE_WS_OUT_DELAY_S 16
|
||||
#define I2S_TRANS_SD_OUT_DELAY 0x00000003
|
||||
#define I2S_TRANS_SD_OUT_DELAY_S 14
|
||||
#define I2S_TRANS_WS_OUT_DELAY 0x00000003
|
||||
#define I2S_TRANS_WS_OUT_DELAY_S 12
|
||||
#define I2S_TRANS_BCK_OUT_DELAY 0x00000003
|
||||
#define I2S_TRANS_BCK_OUT_DELAY_S 10
|
||||
#define I2S_RECE_SD_IN_DELAY 0x00000003
|
||||
#define I2S_RECE_SD_IN_DELAY_S 8
|
||||
#define I2S_RECE_WS_IN_DELAY 0x00000003
|
||||
#define I2S_RECE_WS_IN_DELAY_S 6
|
||||
#define I2S_RECE_BCK_IN_DELAY 0x00000003
|
||||
#define I2S_RECE_BCK_IN_DELAY_S 4
|
||||
#define I2S_TRANS_WS_IN_DELAY 0x00000003
|
||||
#define I2S_TRANS_WS_IN_DELAY_S 2
|
||||
#define I2S_TRANS_BCK_IN_DELAY 0x00000003
|
||||
#define I2S_TRANS_BCK_IN_DELAY_S 0
|
||||
|
||||
#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
|
||||
#define I2S_I2S_RX_FIFO_MOD 0x00000007
|
||||
#define I2S_I2S_RX_FIFO_MOD_S 16
|
||||
#define I2S_I2S_TX_FIFO_MOD 0x00000007
|
||||
#define I2S_I2S_TX_FIFO_MOD_S 13
|
||||
#define I2S_I2S_DSCR_EN (BIT(12))
|
||||
#define I2S_I2S_TX_DATA_NUM 0x0000003F
|
||||
#define I2S_I2S_TX_DATA_NUM_S 6
|
||||
#define I2S_I2S_RX_DATA_NUM 0x0000003F
|
||||
#define I2S_I2S_RX_DATA_NUM_S 0
|
||||
|
||||
|
||||
#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
|
||||
#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
|
||||
#define I2S_I2S_RX_EOF_NUM_S 0
|
||||
|
||||
#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
|
||||
#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
|
||||
#define I2S_I2S_SIGLE_DATA_S 0
|
||||
|
||||
#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
|
||||
#define I2S_RX_CHAN_MOD 0x00000003
|
||||
#define I2S_RX_CHAN_MOD_S 3
|
||||
#define I2S_TX_CHAN_MOD 0x00000007
|
||||
#define I2S_TX_CHAN_MOD_S 0
|
||||
|
||||
|
||||
//From sdio_slv.h
|
||||
|
||||
|
||||
struct sdio_queue
|
||||
{
|
||||
uint32 blocksize:12;
|
||||
uint32 datalen:12;
|
||||
uint32 unused:5;
|
||||
uint32 sub_sof:1;
|
||||
uint32 eof:1;
|
||||
uint32 owner:1;
|
||||
|
||||
uint32 buf_ptr;
|
||||
uint32 next_link_ptr;
|
||||
};
|
||||
|
||||
struct sdio_slave_status_element
|
||||
{
|
||||
uint32 wr_busy:1;
|
||||
uint32 rd_empty :1;
|
||||
uint32 comm_cnt :3;
|
||||
uint32 intr_no :3;
|
||||
uint32 rx_length:16;
|
||||
uint32 res:8;
|
||||
};
|
||||
|
||||
union sdio_slave_status
|
||||
{
|
||||
struct sdio_slave_status_element elm_value;
|
||||
uint32 word_value;
|
||||
};
|
||||
|
||||
#define RX_AVAILIBLE 2
|
||||
#define TX_AVAILIBLE 1
|
||||
#define INIT_STAGE 0
|
||||
|
||||
#define SDIO_QUEUE_LEN 8
|
||||
#define MOSI 0
|
||||
#define MISO 1
|
||||
#define SDIO_DATA_ERROR 6
|
||||
|
||||
#define SLC_INTEREST_EVENT (SLC_TX_EOF_INT_ENA | SLC_RX_EOF_INT_ENA | SLC_RX_UDF_INT_ENA | SLC_TX_DSCR_ERR_INT_ENA)
|
||||
#define TRIG_TOHOST_INT() SET_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0);\
|
||||
CLEAR_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* Copyright (c) Espressif System 2010 - 2012
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
#define PERIPHS_IO_MUX 0x60000800
|
||||
|
||||
#define PERIPHS_IO_MUX_FUNC 0x13
|
||||
#define PERIPHS_IO_MUX_FUNC_S 4
|
||||
#define PERIPHS_IO_MUX_PULLUP BIT7
|
||||
#define PERIPHS_IO_MUX_PULLDWN BIT6
|
||||
#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3
|
||||
#define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2
|
||||
#define PERIPHS_IO_MUX_SLEEP_OE BIT1
|
||||
#define PERIPHS_IO_MUX_OE BIT0
|
||||
|
||||
#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00)
|
||||
#define SPI0_CLK_EQU_SYS_CLK BIT8
|
||||
#define SPI1_CLK_EQU_SYS_CLK BIT9
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04)
|
||||
#define FUNC_MTDI 0
|
||||
#define FUNC_I2SI_DATA 1
|
||||
#define FUNC_HSPIQ_MISO 2
|
||||
#define FUNC_GPIO12 3
|
||||
#define FUNC_UART0_DTR 4
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
|
||||
#define FUNC_MTCK 0
|
||||
#define FUNC_I2SI_BCK 1
|
||||
#define FUNC_HSPID_MOSI 2
|
||||
#define FUNC_GPIO13 3
|
||||
#define FUNC_UART0_CTS 4
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
|
||||
#define FUNC_MTMS 0
|
||||
#define FUNC_I2SI_WS 1
|
||||
#define FUNC_HSPI_CLK 2
|
||||
#define FUNC_GPIO14 3
|
||||
#define FUNC_UART0_DSR 4
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10)
|
||||
#define FUNC_MTDO 0
|
||||
#define FUNC_I2SO_BCK 1
|
||||
#define FUNC_HSPI_CS0 2
|
||||
#define FUNC_GPIO15 3
|
||||
#define FUNC_U0RTS 4
|
||||
#define FUNC_UART0_RTS 4
|
||||
|
||||
#define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14)
|
||||
#define FUNC_U0RXD 0
|
||||
#define FUNC_I2SO_DATA 1
|
||||
#define FUNC_GPIO3 3
|
||||
#define FUNC_CLK_XTAL_BK 4
|
||||
|
||||
#define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18)
|
||||
#define FUNC_U0TXD 0
|
||||
#define FUNC_SPICS1 1
|
||||
#define FUNC_GPIO1 3
|
||||
#define FUNC_CLK_RTC_BK 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c)
|
||||
#define FUNC_SDCLK 0
|
||||
#define FUNC_SPICLK 1
|
||||
#define FUNC_GPIO6 3
|
||||
#define UART1_CTS 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20)
|
||||
#define FUNC_SDDATA0 0
|
||||
#define FUNC_SPIQ_MISO 1
|
||||
#define FUNC_GPIO7 3
|
||||
#define FUNC_U1TXD 4
|
||||
#define FUNC_UART1_TXD 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24)
|
||||
#define FUNC_SDDATA1 0
|
||||
#define FUNC_SPID_MOSI 1
|
||||
#define FUNC_GPIO8 3
|
||||
#define FUNC_U1RXD 4
|
||||
#define FUNC_UART1_RXD 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28)
|
||||
#define FUNC_SDDATA2 0
|
||||
#define FUNC_SPIHD 1
|
||||
#define FUNC_GPIO9 3
|
||||
#define UFNC_HSPIHD 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c)
|
||||
#define FUNC_SDDATA3 0
|
||||
#define FUNC_SPIWP 1
|
||||
#define FUNC_GPIO10 3
|
||||
#define FUNC_HSPIWP 4
|
||||
|
||||
#define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30)
|
||||
#define FUNC_SDCMD 0
|
||||
#define FUNC_SPICS0 1
|
||||
#define FUNC_GPIO11 3
|
||||
#define U1RTS 4
|
||||
#define UART1_RTS 4
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34)
|
||||
#define FUNC_GPIO0 0
|
||||
#define FUNC_SPICS2 1
|
||||
#define FUNC_CLK_OUT 4
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38)
|
||||
#define FUNC_GPIO2 0
|
||||
#define FUNC_I2SO_WS 1
|
||||
#define FUNC_U1TXD_BK 2
|
||||
#define FUNC_UART1_TXD_BK 2
|
||||
#define FUNC_U0TXD_BK 4
|
||||
#define FUNC_UART0_TXD_BK 4
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C)
|
||||
#define FUNC_GPIO4 0
|
||||
#define FUNC_CLK_XTAL 1
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40)
|
||||
#define FUNC_GPIO5 0
|
||||
#define FUNC_CLK_RTC 1
|
||||
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
|
||||
|
||||
//XXX THIS LOOKS WRONG.
|
||||
|
||||
#undef PIN_FUNC_SELECT
|
||||
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \
|
||||
CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC<<PERIPHS_IO_MUX_FUNC_S)); \
|
||||
SET_PERI_REG_MASK(PIN_NAME, (((FUNC&BIT2)<<2)|(FUNC&0x3))<<PERIPHS_IO_MUX_FUNC_S); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#endif //_PIN_MUX_H_
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,958 @@
|
|||
/* Fake6502 CPU emulator core v1.1 *******************
|
||||
* (c)2011 Mike Chambers (miker00lz@gmail.com) *
|
||||
*****************************************************
|
||||
* v1.1 - Small bugfix in BIT opcode, but it was the *
|
||||
* difference between a few games in my NES *
|
||||
* emulator working and being broken! *
|
||||
* I went through the rest carefully again *
|
||||
* after fixing it just to make sure I didn't *
|
||||
* have any other typos! (Dec. 17, 2011) *
|
||||
* *
|
||||
* v1.0 - First release (Nov. 24, 2011) *
|
||||
*****************************************************
|
||||
* LICENSE: This source code is released into the *
|
||||
* public domain, but if you use it please do give *
|
||||
* credit. I put a lot of effort into writing this! *
|
||||
* *
|
||||
*****************************************************
|
||||
* Fake6502 is a MOS Technology 6502 CPU emulation *
|
||||
* engine in C. It was written as part of a Nintendo *
|
||||
* Entertainment System emulator I've been writing. *
|
||||
* *
|
||||
* A couple important things to know about are two *
|
||||
* defines in the code. One is "UNDOCUMENTED" which, *
|
||||
* when defined, allows Fake6502 to compile with *
|
||||
* full support for the more predictable *
|
||||
* undocumented instructions of the 6502. If it is *
|
||||
* undefined, undocumented opcodes just act as NOPs. *
|
||||
* *
|
||||
* The other define is "NES_CPU", which causes the *
|
||||
* code to compile without support for binary-coded *
|
||||
* decimal (BCD) support for the ADC and SBC *
|
||||
* opcodes. The Ricoh 2A03 CPU in the NES does not *
|
||||
* support BCD, but is otherwise identical to the *
|
||||
* standard MOS 6502. (Note that this define is *
|
||||
* enabled in this file if you haven't changed it *
|
||||
* yourself. If you're not emulating a NES, you *
|
||||
* should comment it out.) *
|
||||
* *
|
||||
* If you do discover an error in timing accuracy, *
|
||||
* or operation in general please e-mail me at the *
|
||||
* address above so that I can fix it. Thank you! *
|
||||
* *
|
||||
*****************************************************
|
||||
* Usage: *
|
||||
* *
|
||||
* Fake6502 requires you to provide two external *
|
||||
* functions: *
|
||||
* *
|
||||
* uint8_t read6502(uint16_t address) *
|
||||
* void write6502(uint16_t address, uint8_t value) *
|
||||
* *
|
||||
* You may optionally pass Fake6502 the pointer to a *
|
||||
* function which you want to be called after every *
|
||||
* emulated instruction. This function should be a *
|
||||
* void with no parameters expected to be passed to *
|
||||
* it. *
|
||||
* *
|
||||
* This can be very useful. For example, in a NES *
|
||||
* emulator, you check the number of clock ticks *
|
||||
* that have passed so you can know when to handle *
|
||||
* APU events. *
|
||||
* *
|
||||
* To pass Fake6502 this pointer, use the *
|
||||
* hookexternal(void *funcptr) function provided. *
|
||||
* *
|
||||
* To disable the hook later, pass NULL to it. *
|
||||
*****************************************************
|
||||
* Useful functions in this emulator: *
|
||||
* *
|
||||
* void reset6502() *
|
||||
* - Call this once before you begin execution. *
|
||||
* *
|
||||
* void exec6502(uint32_t tickcount) *
|
||||
* - Execute 6502 code up to the next specified *
|
||||
* count of clock ticks. *
|
||||
* *
|
||||
* void step6502() *
|
||||
* - Execute a single instrution. *
|
||||
* *
|
||||
* void irq6502() *
|
||||
* - Trigger a hardware IRQ in the 6502 core. *
|
||||
* *
|
||||
* void nmi6502() *
|
||||
* - Trigger an NMI in the 6502 core. *
|
||||
* *
|
||||
* void hookexternal(void *funcptr) *
|
||||
* - Pass a pointer to a void function taking no *
|
||||
* parameters. This will cause Fake6502 to call *
|
||||
* that function once after each emulated *
|
||||
* instruction. *
|
||||
* *
|
||||
*****************************************************
|
||||
* Useful variables in this emulator: *
|
||||
* *
|
||||
* uint32_t clockticks6502 *
|
||||
* - A running total of the emulated cycle count. *
|
||||
* *
|
||||
* *
|
||||
*****************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
//6502 defines
|
||||
// #define UNDOCUMENTED //when this is defined, undocumented opcodes are handled.
|
||||
//otherwise, they're simply treated as NOPs.
|
||||
|
||||
// #define NES_CPU //when this is defined, the binary-coded decimal (BCD)
|
||||
//status flag is not honored by ADC and SBC. the 2A03
|
||||
//CPU in the Nintendo Entertainment System does not
|
||||
//support BCD operation.
|
||||
|
||||
#define FLAG_CARRY 0x01
|
||||
#define FLAG_ZERO 0x02
|
||||
#define FLAG_INTERRUPT 0x04
|
||||
#define FLAG_DECIMAL 0x08
|
||||
#define FLAG_BREAK 0x10
|
||||
#define FLAG_CONSTANT 0x20
|
||||
#define FLAG_OVERFLOW 0x40
|
||||
#define FLAG_SIGN 0x80
|
||||
|
||||
#define BASE_STACK 0x100
|
||||
|
||||
#define saveaccum(n) a = (uint8_t)((n) & 0x00FF)
|
||||
|
||||
|
||||
//flag modifier macros
|
||||
#define setcarry() status |= FLAG_CARRY
|
||||
#define clearcarry() status &= (~FLAG_CARRY)
|
||||
#define setzero() status |= FLAG_ZERO
|
||||
#define clearzero() status &= (~FLAG_ZERO)
|
||||
#define setinterrupt() status |= FLAG_INTERRUPT
|
||||
#define clearinterrupt() status &= (~FLAG_INTERRUPT)
|
||||
#define setdecimal() status |= FLAG_DECIMAL
|
||||
#define cleardecimal() status &= (~FLAG_DECIMAL)
|
||||
#define setoverflow() status |= FLAG_OVERFLOW
|
||||
#define clearoverflow() status &= (~FLAG_OVERFLOW)
|
||||
#define setsign() status |= FLAG_SIGN
|
||||
#define clearsign() status &= (~FLAG_SIGN)
|
||||
|
||||
|
||||
//flag calculation macros
|
||||
#define zerocalc(n) {\
|
||||
if ((n) & 0x00FF) clearzero();\
|
||||
else setzero();\
|
||||
}
|
||||
|
||||
#define signcalc(n) {\
|
||||
if ((n) & 0x0080) setsign();\
|
||||
else clearsign();\
|
||||
}
|
||||
|
||||
#define carrycalc(n) {\
|
||||
if ((n) & 0xFF00) setcarry();\
|
||||
else clearcarry();\
|
||||
}
|
||||
|
||||
#define overflowcalc(n, m, o) { /* n = result, m = accumulator, o = memory */ \
|
||||
if (((n) ^ (uint16_t)(m)) & ((n) ^ (o)) & 0x0080) setoverflow();\
|
||||
else clearoverflow();\
|
||||
}
|
||||
|
||||
|
||||
//6502 CPU registers
|
||||
uint16_t pc;
|
||||
uint8_t sp, a, x, y, status;
|
||||
|
||||
|
||||
//helper variables
|
||||
uint32_t clockticks6502 = 0, clockgoal6502 = 0;
|
||||
uint16_t oldpc, ea, reladdr, value, result;
|
||||
uint8_t opcode, oldstatus;
|
||||
|
||||
//externally supplied functions
|
||||
extern uint8_t read6502(uint16_t address);
|
||||
extern void write6502(uint16_t address, uint8_t value);
|
||||
|
||||
//a few general functions used by various other functions
|
||||
void push16(uint16_t pushval) {
|
||||
write6502(BASE_STACK + sp, (pushval >> 8) & 0xFF);
|
||||
write6502(BASE_STACK + ((sp - 1) & 0xFF), pushval & 0xFF);
|
||||
sp -= 2;
|
||||
}
|
||||
|
||||
void push8(uint8_t pushval) {
|
||||
write6502(BASE_STACK + sp--, pushval);
|
||||
}
|
||||
|
||||
uint16_t pull16() {
|
||||
uint16_t temp16;
|
||||
temp16 = read6502(BASE_STACK + ((sp + 1) & 0xFF)) | ((uint16_t)read6502(BASE_STACK + ((sp + 2) & 0xFF)) << 8);
|
||||
sp += 2;
|
||||
return(temp16);
|
||||
}
|
||||
|
||||
uint8_t pull8() {
|
||||
return (read6502(BASE_STACK + ++sp));
|
||||
}
|
||||
|
||||
void reset6502() {
|
||||
// pc = ((uint16_t)read6502(0xfffc) | ((uint16_t)read6502(0xfffd) << 8));
|
||||
pc = 0xff00;
|
||||
|
||||
a = 0;
|
||||
x = 0;
|
||||
y = 0;
|
||||
sp = 0xFF;
|
||||
status |= FLAG_CONSTANT | FLAG_BREAK;
|
||||
}
|
||||
|
||||
|
||||
static void (*addrtable[256])();
|
||||
static void (*optable[256])();
|
||||
uint8_t penaltyop, penaltyaddr;
|
||||
|
||||
//addressing mode functions, calculates effective addresses
|
||||
static void imp() { //implied
|
||||
}
|
||||
|
||||
static void acc() { //accumulator
|
||||
}
|
||||
|
||||
static void imm() { //immediate
|
||||
ea = pc++;
|
||||
}
|
||||
|
||||
static void zp() { //zero-page
|
||||
ea = (uint16_t)read6502((uint16_t)pc++);
|
||||
}
|
||||
|
||||
static void zpx() { //zero-page,X
|
||||
ea = ((uint16_t)read6502((uint16_t)pc++) + (uint16_t)x) & 0xFF; //zero-page wraparound
|
||||
}
|
||||
|
||||
static void zpy() { //zero-page,Y
|
||||
ea = ((uint16_t)read6502((uint16_t)pc++) + (uint16_t)y) & 0xFF; //zero-page wraparound
|
||||
}
|
||||
|
||||
static void rel() { //relative for branch ops (8-bit immediate value, sign-extended)
|
||||
reladdr = (uint16_t)read6502(pc++);
|
||||
if (reladdr & 0x80) reladdr |= 0xFF00;
|
||||
}
|
||||
|
||||
static void abso() { //absolute
|
||||
ea = (uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8);
|
||||
pc += 2;
|
||||
}
|
||||
|
||||
static void absx() { //absolute,X
|
||||
uint16_t startpage;
|
||||
ea = ((uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8));
|
||||
startpage = ea & 0xFF00;
|
||||
ea += (uint16_t)x;
|
||||
|
||||
if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes
|
||||
penaltyaddr = 1;
|
||||
}
|
||||
|
||||
pc += 2;
|
||||
}
|
||||
|
||||
static void absy() { //absolute,Y
|
||||
uint16_t startpage;
|
||||
ea = ((uint16_t)read6502(pc) | ((uint16_t)read6502(pc+1) << 8));
|
||||
startpage = ea & 0xFF00;
|
||||
ea += (uint16_t)y;
|
||||
|
||||
if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes
|
||||
penaltyaddr = 1;
|
||||
}
|
||||
|
||||
pc += 2;
|
||||
}
|
||||
|
||||
static void ind() { //indirect
|
||||
uint16_t eahelp, eahelp2;
|
||||
eahelp = (uint16_t)read6502(pc) | (uint16_t)((uint16_t)read6502(pc+1) << 8);
|
||||
eahelp2 = (eahelp & 0xFF00) | ((eahelp + 1) & 0x00FF); //replicate 6502 page-boundary wraparound bug
|
||||
ea = (uint16_t)read6502(eahelp) | ((uint16_t)read6502(eahelp2) << 8);
|
||||
pc += 2;
|
||||
}
|
||||
|
||||
static void indx() { // (indirect,X)
|
||||
uint16_t eahelp;
|
||||
eahelp = (uint16_t)(((uint16_t)read6502(pc++) + (uint16_t)x) & 0xFF); //zero-page wraparound for table pointer
|
||||
ea = (uint16_t)read6502(eahelp & 0x00FF) | ((uint16_t)read6502((eahelp+1) & 0x00FF) << 8);
|
||||
}
|
||||
|
||||
static void indy() { // (indirect),Y
|
||||
uint16_t eahelp, eahelp2, startpage;
|
||||
eahelp = (uint16_t)read6502(pc++);
|
||||
eahelp2 = (eahelp & 0xFF00) | ((eahelp + 1) & 0x00FF); //zero-page wraparound
|
||||
ea = (uint16_t)read6502(eahelp) | ((uint16_t)read6502(eahelp2) << 8);
|
||||
startpage = ea & 0xFF00;
|
||||
ea += (uint16_t)y;
|
||||
|
||||
if (startpage != (ea & 0xFF00)) { //one cycle penlty for page-crossing on some opcodes
|
||||
penaltyaddr = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static uint16_t getvalue() {
|
||||
if (addrtable[opcode] == acc) return((uint16_t)a);
|
||||
else return((uint16_t)read6502(ea));
|
||||
}
|
||||
|
||||
static uint16_t getvalue16() {
|
||||
return((uint16_t)read6502(ea) | ((uint16_t)read6502(ea+1) << 8));
|
||||
}
|
||||
|
||||
static void putvalue(uint16_t saveval) {
|
||||
if (addrtable[opcode] == acc) a = (uint8_t)(saveval & 0x00FF);
|
||||
else write6502(ea, (saveval & 0x00FF));
|
||||
}
|
||||
|
||||
|
||||
//instruction handler functions
|
||||
static void adc() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
result = (uint16_t)a + value + (uint16_t)(status & FLAG_CARRY);
|
||||
|
||||
carrycalc(result);
|
||||
zerocalc(result);
|
||||
overflowcalc(result, a, value);
|
||||
signcalc(result);
|
||||
|
||||
#ifndef NES_CPU
|
||||
if (status & FLAG_DECIMAL) {
|
||||
clearcarry();
|
||||
|
||||
if ((a & 0x0F) > 0x09) {
|
||||
a += 0x06;
|
||||
}
|
||||
if ((a & 0xF0) > 0x90) {
|
||||
a += 0x60;
|
||||
setcarry();
|
||||
}
|
||||
|
||||
clockticks6502++;
|
||||
}
|
||||
#endif
|
||||
|
||||
saveaccum(result);
|
||||
}
|
||||
|
||||
static void and() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
result = (uint16_t)a & value;
|
||||
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
saveaccum(result);
|
||||
}
|
||||
|
||||
static void asl() {
|
||||
value = getvalue();
|
||||
result = value << 1;
|
||||
|
||||
carrycalc(result);
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void bcc() {
|
||||
if ((status & FLAG_CARRY) == 0) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void bcs() {
|
||||
if ((status & FLAG_CARRY) == FLAG_CARRY) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void beq() {
|
||||
if ((status & FLAG_ZERO) == FLAG_ZERO) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void bit() {
|
||||
value = getvalue();
|
||||
result = (uint16_t)a & value;
|
||||
|
||||
zerocalc(result);
|
||||
status = (status & 0x3F) | (uint8_t)(value & 0xC0);
|
||||
}
|
||||
|
||||
static void bmi() {
|
||||
if ((status & FLAG_SIGN) == FLAG_SIGN) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void bne() {
|
||||
if ((status & FLAG_ZERO) == 0) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void bpl() {
|
||||
if ((status & FLAG_SIGN) == 0) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void brk() {
|
||||
pc++;
|
||||
push16(pc); //push next instruction address onto stack
|
||||
push8(status | FLAG_BREAK); //push CPU status to stack
|
||||
setinterrupt(); //set interrupt flag
|
||||
pc = (uint16_t)read6502(0xFFFE) | ((uint16_t)read6502(0xFFFF) << 8);
|
||||
}
|
||||
|
||||
static void bvc() {
|
||||
if ((status & FLAG_OVERFLOW) == 0) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void bvs() {
|
||||
if ((status & FLAG_OVERFLOW) == FLAG_OVERFLOW) {
|
||||
oldpc = pc;
|
||||
pc += reladdr;
|
||||
if ((oldpc & 0xFF00) != (pc & 0xFF00)) clockticks6502 += 2; //check if jump crossed a page boundary
|
||||
else clockticks6502++;
|
||||
}
|
||||
}
|
||||
|
||||
static void clc() {
|
||||
clearcarry();
|
||||
}
|
||||
|
||||
static void cld() {
|
||||
cleardecimal();
|
||||
}
|
||||
|
||||
static void cli() {
|
||||
clearinterrupt();
|
||||
}
|
||||
|
||||
static void clv() {
|
||||
clearoverflow();
|
||||
}
|
||||
|
||||
static void cmp() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
result = (uint16_t)a - value;
|
||||
|
||||
if (a >= (uint8_t)(value & 0x00FF)) setcarry();
|
||||
else clearcarry();
|
||||
if (a == (uint8_t)(value & 0x00FF)) setzero();
|
||||
else clearzero();
|
||||
signcalc(result);
|
||||
}
|
||||
|
||||
static void cpx() {
|
||||
value = getvalue();
|
||||
result = (uint16_t)x - value;
|
||||
|
||||
if (x >= (uint8_t)(value & 0x00FF)) setcarry();
|
||||
else clearcarry();
|
||||
if (x == (uint8_t)(value & 0x00FF)) setzero();
|
||||
else clearzero();
|
||||
signcalc(result);
|
||||
}
|
||||
|
||||
static void cpy() {
|
||||
value = getvalue();
|
||||
result = (uint16_t)y - value;
|
||||
|
||||
if (y >= (uint8_t)(value & 0x00FF)) setcarry();
|
||||
else clearcarry();
|
||||
if (y == (uint8_t)(value & 0x00FF)) setzero();
|
||||
else clearzero();
|
||||
signcalc(result);
|
||||
}
|
||||
|
||||
static void dec() {
|
||||
value = getvalue();
|
||||
result = value - 1;
|
||||
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void dex() {
|
||||
x--;
|
||||
|
||||
zerocalc(x);
|
||||
signcalc(x);
|
||||
}
|
||||
|
||||
static void dey() {
|
||||
y--;
|
||||
|
||||
zerocalc(y);
|
||||
signcalc(y);
|
||||
}
|
||||
|
||||
static void eor() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
result = (uint16_t)a ^ value;
|
||||
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
saveaccum(result);
|
||||
}
|
||||
|
||||
static void inc() {
|
||||
value = getvalue();
|
||||
result = value + 1;
|
||||
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void inx() {
|
||||
x++;
|
||||
|
||||
zerocalc(x);
|
||||
signcalc(x);
|
||||
}
|
||||
|
||||
static void iny() {
|
||||
y++;
|
||||
|
||||
zerocalc(y);
|
||||
signcalc(y);
|
||||
}
|
||||
|
||||
static void jmp() {
|
||||
pc = ea;
|
||||
}
|
||||
|
||||
static void jsr() {
|
||||
push16(pc - 1);
|
||||
pc = ea;
|
||||
}
|
||||
|
||||
static void lda() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
a = (uint8_t)(value & 0x00FF);
|
||||
|
||||
zerocalc(a);
|
||||
signcalc(a);
|
||||
}
|
||||
|
||||
static void ldx() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
x = (uint8_t)(value & 0x00FF);
|
||||
|
||||
zerocalc(x);
|
||||
signcalc(x);
|
||||
}
|
||||
|
||||
static void ldy() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
y = (uint8_t)(value & 0x00FF);
|
||||
|
||||
zerocalc(y);
|
||||
signcalc(y);
|
||||
}
|
||||
|
||||
static void lsr() {
|
||||
value = getvalue();
|
||||
result = value >> 1;
|
||||
|
||||
if (value & 1) setcarry();
|
||||
else clearcarry();
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void nop() {
|
||||
switch (opcode) {
|
||||
case 0x1C:
|
||||
case 0x3C:
|
||||
case 0x5C:
|
||||
case 0x7C:
|
||||
case 0xDC:
|
||||
case 0xFC:
|
||||
penaltyop = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void ora() {
|
||||
penaltyop = 1;
|
||||
value = getvalue();
|
||||
result = (uint16_t)a | value;
|
||||
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
saveaccum(result);
|
||||
}
|
||||
|
||||
static void pha() {
|
||||
push8(a);
|
||||
}
|
||||
|
||||
static void php() {
|
||||
push8(status | FLAG_BREAK);
|
||||
}
|
||||
|
||||
static void pla() {
|
||||
a = pull8();
|
||||
|
||||
zerocalc(a);
|
||||
signcalc(a);
|
||||
}
|
||||
|
||||
static void plp() {
|
||||
status = pull8() | FLAG_CONSTANT;
|
||||
}
|
||||
|
||||
static void rol() {
|
||||
value = getvalue();
|
||||
result = (value << 1) | (status & FLAG_CARRY);
|
||||
|
||||
carrycalc(result);
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void ror() {
|
||||
value = getvalue();
|
||||
result = (value >> 1) | ((status & FLAG_CARRY) << 7);
|
||||
|
||||
if (value & 1) setcarry();
|
||||
else clearcarry();
|
||||
zerocalc(result);
|
||||
signcalc(result);
|
||||
|
||||
putvalue(result);
|
||||
}
|
||||
|
||||
static void rti() {
|
||||
status = pull8();
|
||||
value = pull16();
|
||||
pc = value;
|
||||
}
|
||||
|
||||
static void rts() {
|
||||
value = pull16();
|
||||
pc = value + 1;
|
||||
}
|
||||
|
||||
static void sbc() {
|
||||
penaltyop = 1;
|
||||
value = getvalue() ^ 0x00FF;
|
||||
result = (uint16_t)a + value + (uint16_t)(status & FLAG_CARRY);
|
||||
|
||||
carrycalc(result);
|
||||
zerocalc(result);
|
||||
overflowcalc(result, a, value);
|
||||
signcalc(result);
|
||||
|
||||
#ifndef NES_CPU
|
||||
if (status & FLAG_DECIMAL) {
|
||||
clearcarry();
|
||||
|
||||
a -= 0x66;
|
||||
if ((a & 0x0F) > 0x09) {
|
||||
a += 0x06;
|
||||
}
|
||||
if ((a & 0xF0) > 0x90) {
|
||||
a += 0x60;
|
||||
setcarry();
|
||||
}
|
||||
|
||||
clockticks6502++;
|
||||
}
|
||||
#endif
|
||||
|
||||
saveaccum(result);
|
||||
}
|
||||
|
||||
static void sec() {
|
||||
setcarry();
|
||||
}
|
||||
|
||||
static void sed() {
|
||||
setdecimal();
|
||||
}
|
||||
|
||||
static void sei() {
|
||||
setinterrupt();
|
||||
}
|
||||
|
||||
static void sta() {
|
||||
putvalue(a);
|
||||
}
|
||||
|
||||
static void stx() {
|
||||
putvalue(x);
|
||||
}
|
||||
|
||||
static void sty() {
|
||||
putvalue(y);
|
||||
}
|
||||
|
||||
static void tax() {
|
||||
x = a;
|
||||
|
||||
zerocalc(x);
|
||||
signcalc(x);
|
||||
}
|
||||
|
||||
static void tay() {
|
||||
y = a;
|
||||
|
||||
zerocalc(y);
|
||||
signcalc(y);
|
||||
}
|
||||
|
||||
static void tsx() {
|
||||
x = sp;
|
||||
|
||||
zerocalc(x);
|
||||
signcalc(x);
|
||||
}
|
||||
|
||||
static void txa() {
|
||||
a = x;
|
||||
|
||||
zerocalc(a);
|
||||
signcalc(a);
|
||||
}
|
||||
|
||||
static void txs() {
|
||||
sp = x;
|
||||
}
|
||||
|
||||
static void tya() {
|
||||
a = y;
|
||||
|
||||
zerocalc(a);
|
||||
signcalc(a);
|
||||
}
|
||||
|
||||
//undocumented instructions
|
||||
#ifdef UNDOCUMENTED
|
||||
static void lax() {
|
||||
lda();
|
||||
ldx();
|
||||
}
|
||||
|
||||
static void sax() {
|
||||
sta();
|
||||
stx();
|
||||
putvalue(a & x);
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void dcp() {
|
||||
dec();
|
||||
cmp();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void isb() {
|
||||
inc();
|
||||
sbc();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void slo() {
|
||||
asl();
|
||||
ora();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void rla() {
|
||||
rol();
|
||||
and();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void sre() {
|
||||
lsr();
|
||||
eor();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
|
||||
static void rra() {
|
||||
ror();
|
||||
adc();
|
||||
if (penaltyop && penaltyaddr) clockticks6502--;
|
||||
}
|
||||
#else
|
||||
#define lax nop
|
||||
#define sax nop
|
||||
#define dcp nop
|
||||
#define isb nop
|
||||
#define slo nop
|
||||
#define rla nop
|
||||
#define sre nop
|
||||
#define rra nop
|
||||
#endif
|
||||
|
||||
|
||||
static void (*addrtable[256])() = {
|
||||
/* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */
|
||||
/* 0 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 0 */
|
||||
/* 1 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 1 */
|
||||
/* 2 */ abso, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 2 */
|
||||
/* 3 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 3 */
|
||||
/* 4 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, abso, abso, abso, abso, /* 4 */
|
||||
/* 5 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 5 */
|
||||
/* 6 */ imp, indx, imp, indx, zp, zp, zp, zp, imp, imm, acc, imm, ind, abso, abso, abso, /* 6 */
|
||||
/* 7 */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* 7 */
|
||||
/* 8 */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* 8 */
|
||||
/* 9 */ rel, indy, imp, indy, zpx, zpx, zpy, zpy, imp, absy, imp, absy, absx, absx, absy, absy, /* 9 */
|
||||
/* A */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* A */
|
||||
/* B */ rel, indy, imp, indy, zpx, zpx, zpy, zpy, imp, absy, imp, absy, absx, absx, absy, absy, /* B */
|
||||
/* C */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* C */
|
||||
/* D */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx, /* D */
|
||||
/* E */ imm, indx, imm, indx, zp, zp, zp, zp, imp, imm, imp, imm, abso, abso, abso, abso, /* E */
|
||||
/* F */ rel, indy, imp, indy, zpx, zpx, zpx, zpx, imp, absy, imp, absy, absx, absx, absx, absx /* F */
|
||||
};
|
||||
|
||||
static void (*optable[256])() = {
|
||||
/* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */
|
||||
/* 0 */ brk, ora, nop, slo, nop, ora, asl, slo, php, ora, asl, nop, nop, ora, asl, slo, /* 0 */
|
||||
/* 1 */ bpl, ora, nop, slo, nop, ora, asl, slo, clc, ora, nop, slo, nop, ora, asl, slo, /* 1 */
|
||||
/* 2 */ jsr, and, nop, rla, bit, and, rol, rla, plp, and, rol, nop, bit, and, rol, rla, /* 2 */
|
||||
/* 3 */ bmi, and, nop, rla, nop, and, rol, rla, sec, and, nop, rla, nop, and, rol, rla, /* 3 */
|
||||
/* 4 */ rti, eor, nop, sre, nop, eor, lsr, sre, pha, eor, lsr, nop, jmp, eor, lsr, sre, /* 4 */
|
||||
/* 5 */ bvc, eor, nop, sre, nop, eor, lsr, sre, cli, eor, nop, sre, nop, eor, lsr, sre, /* 5 */
|
||||
/* 6 */ rts, adc, nop, rra, nop, adc, ror, rra, pla, adc, ror, nop, jmp, adc, ror, rra, /* 6 */
|
||||
/* 7 */ bvs, adc, nop, rra, nop, adc, ror, rra, sei, adc, nop, rra, nop, adc, ror, rra, /* 7 */
|
||||
/* 8 */ nop, sta, nop, sax, sty, sta, stx, sax, dey, nop, txa, nop, sty, sta, stx, sax, /* 8 */
|
||||
/* 9 */ bcc, sta, nop, nop, sty, sta, stx, sax, tya, sta, txs, nop, nop, sta, nop, nop, /* 9 */
|
||||
/* A */ ldy, lda, ldx, lax, ldy, lda, ldx, lax, tay, lda, tax, nop, ldy, lda, ldx, lax, /* A */
|
||||
/* B */ bcs, lda, nop, lax, ldy, lda, ldx, lax, clv, lda, tsx, lax, ldy, lda, ldx, lax, /* B */
|
||||
/* C */ cpy, cmp, nop, dcp, cpy, cmp, dec, dcp, iny, cmp, dex, nop, cpy, cmp, dec, dcp, /* C */
|
||||
/* D */ bne, cmp, nop, dcp, nop, cmp, dec, dcp, cld, cmp, nop, dcp, nop, cmp, dec, dcp, /* D */
|
||||
/* E */ cpx, sbc, nop, isb, cpx, sbc, inc, isb, inx, sbc, nop, sbc, cpx, sbc, inc, isb, /* E */
|
||||
/* F */ beq, sbc, nop, isb, nop, sbc, inc, isb, sed, sbc, nop, isb, nop, sbc, inc, isb /* F */
|
||||
};
|
||||
|
||||
static const uint8_t ticktable[256] = {
|
||||
/* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | */
|
||||
/* 0 */ 7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6, /* 0 */
|
||||
/* 1 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 1 */
|
||||
/* 2 */ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 4, 4, 6, 6, /* 2 */
|
||||
/* 3 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 3 */
|
||||
/* 4 */ 6, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 3, 4, 6, 6, /* 4 */
|
||||
/* 5 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 5 */
|
||||
/* 6 */ 6, 6, 2, 8, 3, 3, 5, 5, 4, 2, 2, 2, 5, 4, 6, 6, /* 6 */
|
||||
/* 7 */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* 7 */
|
||||
/* 8 */ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4, /* 8 */
|
||||
/* 9 */ 2, 6, 2, 6, 4, 4, 4, 4, 2, 5, 2, 5, 5, 5, 5, 5, /* 9 */
|
||||
/* A */ 2, 6, 2, 6, 3, 3, 3, 3, 2, 2, 2, 2, 4, 4, 4, 4, /* A */
|
||||
/* B */ 2, 5, 2, 5, 4, 4, 4, 4, 2, 4, 2, 4, 4, 4, 4, 4, /* B */
|
||||
/* C */ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6, /* C */
|
||||
/* D */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, /* D */
|
||||
/* E */ 2, 6, 2, 8, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 6, /* E */
|
||||
/* F */ 2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7 /* F */
|
||||
};
|
||||
|
||||
|
||||
void nmi6502() {
|
||||
push16(pc);
|
||||
push8(status);
|
||||
status |= FLAG_INTERRUPT;
|
||||
pc = (uint16_t)read6502(0xFFFA) | ((uint16_t)read6502(0xFFFB) << 8);
|
||||
}
|
||||
|
||||
uint16_t getPC() {
|
||||
return pc;
|
||||
}
|
||||
|
||||
void irq6502() {
|
||||
push16(pc);
|
||||
push8(status);
|
||||
status |= FLAG_INTERRUPT;
|
||||
pc = (uint16_t)read6502(0xFFFE) | ((uint16_t)read6502(0xFFFF) << 8);
|
||||
}
|
||||
|
||||
uint8_t callexternal = 0;
|
||||
void (*loopexternal)();
|
||||
|
||||
void exec6502(uint32_t tickcount) {
|
||||
clockgoal6502 += tickcount;
|
||||
|
||||
while (clockticks6502 < clockgoal6502) {
|
||||
opcode = read6502(pc++);
|
||||
status |= FLAG_CONSTANT;
|
||||
|
||||
penaltyop = 0;
|
||||
penaltyaddr = 0;
|
||||
|
||||
(*addrtable[opcode])();
|
||||
(*optable[opcode])();
|
||||
clockticks6502 += ticktable[opcode];
|
||||
if (penaltyop && penaltyaddr) clockticks6502++;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void step6502() {
|
||||
opcode = read6502(pc++);
|
||||
status |= FLAG_CONSTANT;
|
||||
|
||||
penaltyop = 0;
|
||||
penaltyaddr = 0;
|
||||
|
||||
(*addrtable[opcode])();
|
||||
(*optable[opcode])();
|
||||
clockticks6502 += ticktable[opcode];
|
||||
if (penaltyop && penaltyaddr) clockticks6502++;
|
||||
clockgoal6502 = clockticks6502;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/******************************************************************************
|
||||
* Copyright 2013-2015 Espressif Systems
|
||||
* 2015 <>< Charles Lohr
|
||||
* 2017 Hrvoje Cavrak
|
||||
*/
|
||||
|
||||
#include "slc_register.h"
|
||||
#include <c_types.h>
|
||||
#include "user_interface.h"
|
||||
#include "pin_mux_register.h"
|
||||
#include "signetics_video_rom.h"
|
||||
#include <dmastuff.h>
|
||||
|
||||
#define WS_I2S_BCK 1
|
||||
#define WS_I2S_DIV 2
|
||||
|
||||
#define LINE_BUFFER_LENGTH 160
|
||||
#define PAL_LINES 625
|
||||
#define LINETYPES 6
|
||||
|
||||
#define SYNC_LEVEL 0x99999999
|
||||
#define WHITE_LEVEL 0xffffffff
|
||||
#define BLACK_LEVEL 0xbbbbbbbb
|
||||
|
||||
extern uint8_t terminal_ram[40 * 24];
|
||||
|
||||
uint32_t i2s_dma_buffer[LINE_BUFFER_LENGTH*LINETYPES];
|
||||
static struct sdio_queue i2sBufDesc[PAL_LINES];
|
||||
|
||||
int current_pixel_line;
|
||||
|
||||
LOCAL void slc_isr(void) {
|
||||
struct sdio_queue *finishedDesc;
|
||||
uint32 slc_intr_status;
|
||||
uint8_t x;
|
||||
|
||||
//Grab int status
|
||||
slc_intr_status = READ_PERI_REG(SLC_INT_STATUS);
|
||||
|
||||
//clear all intr flags
|
||||
WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
|
||||
|
||||
if (slc_intr_status & SLC_RX_EOF_INT_ST) {
|
||||
//The DMA subsystem is done with this block: Push it on the queue so it can be re-used.
|
||||
finishedDesc=(struct sdio_queue*)READ_PERI_REG(SLC_RX_EOF_DES_ADDR);
|
||||
|
||||
struct sdio_queue * next = (struct sdio_queue *)finishedDesc->next_link_ptr;
|
||||
uint32_t * buffer_pointer = (uint32_t*)next->buf_ptr;
|
||||
|
||||
if( next->unused > 1)
|
||||
{
|
||||
current_pixel_line = 0;
|
||||
}
|
||||
|
||||
else if( next->unused )
|
||||
{
|
||||
uint8_t pixel_column = 30;
|
||||
|
||||
/* Determines which terminal line we are currently rendering, 192 pixel lines >> 3 = 24 text lines. Each is 40 bytes long. */
|
||||
uint8_t *terminal_line = &terminal_ram[40 * (current_pixel_line >> 3)];
|
||||
|
||||
/* 8 banks (one for each char line) of 192 bytes contain character definitions. Each character is pre-encoded to optimize performance. */
|
||||
uint32_t *character_row = &Signetics_2513_Modulated_Video_ROM[(current_pixel_line & 0b111) * 192];
|
||||
|
||||
/* For each character in the line */
|
||||
for( x = 0; x < 40; x++ )
|
||||
{
|
||||
|
||||
/* Get pre-encoded character definition from array */
|
||||
uint32_t *character = &character_row[3*(terminal_line[x] & 0x3F)];
|
||||
|
||||
/* Use loop unrolling to improve performance */
|
||||
buffer_pointer[pixel_column++] = *character++;
|
||||
buffer_pointer[pixel_column++] = *character++;
|
||||
buffer_pointer[pixel_column++] = *character++;
|
||||
}
|
||||
|
||||
current_pixel_line++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* PAL signals */
|
||||
#define SHORT_SYNC_INTERVAL 5
|
||||
#define LONG_SYNC_INTERVAL 75
|
||||
#define BACK_PORCH 20
|
||||
#define NORMAL_SYNC_INTERVAL 10
|
||||
#define LINE_SIGNAL_INTERVAL 150
|
||||
|
||||
#define SHORT_SYNC 0
|
||||
#define LONG_SYNC 1
|
||||
#define BLACK_SIGNAL 2
|
||||
#define SHORT_TO_LONG 3
|
||||
#define LONG_TO_SHORT 4
|
||||
#define LINE_SIGNAL 5
|
||||
|
||||
//Initialize I2S subsystem for DMA circular buffer use
|
||||
void ICACHE_FLASH_ATTR testi2s_init() {
|
||||
int x, y;
|
||||
|
||||
uint32_t * line = i2s_dma_buffer;
|
||||
|
||||
uint8_t single_line_timings[20] = {
|
||||
SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL,
|
||||
LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL,
|
||||
NORMAL_SYNC_INTERVAL, LINE_SIGNAL_INTERVAL,
|
||||
SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL,
|
||||
LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL, LONG_SYNC_INTERVAL, SHORT_SYNC_INTERVAL,
|
||||
NORMAL_SYNC_INTERVAL, LINE_SIGNAL_INTERVAL
|
||||
};
|
||||
|
||||
uint32_t single_line_levels[20] = {
|
||||
SYNC_LEVEL, BLACK_LEVEL, SYNC_LEVEL, BLACK_LEVEL,
|
||||
SYNC_LEVEL, BLACK_LEVEL, SYNC_LEVEL, BLACK_LEVEL,
|
||||
SYNC_LEVEL, BLACK_LEVEL,
|
||||
SYNC_LEVEL, BLACK_LEVEL, SYNC_LEVEL, BLACK_LEVEL,
|
||||
SYNC_LEVEL, BLACK_LEVEL, SYNC_LEVEL, BLACK_LEVEL,
|
||||
SYNC_LEVEL, BLACK_LEVEL,
|
||||
};
|
||||
|
||||
uint8_t i, signal;
|
||||
|
||||
for (signal = 0; signal < 20; signal++)
|
||||
for (i=0; i < single_line_timings[signal]; i++, *line++ = single_line_levels[signal]) ;
|
||||
|
||||
|
||||
|
||||
/* Reference: http://martin.hinner.info/vga/pal_tv_diagram_interlace.jpg */
|
||||
|
||||
uint16_t pal_lines[42] = {
|
||||
/* Lines Pattern Unused */
|
||||
3, LONG_SYNC, 0,
|
||||
4, LONG_TO_SHORT, 0,
|
||||
6, SHORT_SYNC, 0,
|
||||
|
||||
57, BLACK_SIGNAL, 0,
|
||||
250, LINE_SIGNAL, 1,
|
||||
311, BLACK_SIGNAL, 0,
|
||||
|
||||
313, SHORT_SYNC, 0,
|
||||
314, SHORT_TO_LONG, 0,
|
||||
316, LONG_SYNC, 0,
|
||||
318, SHORT_SYNC, 0,
|
||||
|
||||
370, BLACK_SIGNAL, 0,
|
||||
562, LINE_SIGNAL, 1,
|
||||
623, BLACK_SIGNAL, 0,
|
||||
|
||||
626, SHORT_SYNC, 0,
|
||||
};
|
||||
|
||||
uint16_t *pal_line = pal_lines;
|
||||
|
||||
//Initialize DMA buffer descriptors in such a way that they will form a circular
|
||||
//buffer.
|
||||
for (x=0; x<PAL_LINES; x++) {
|
||||
i2sBufDesc[x].owner=1;
|
||||
i2sBufDesc[x].eof=1;
|
||||
i2sBufDesc[x].sub_sof=0;
|
||||
i2sBufDesc[x].datalen=LINE_BUFFER_LENGTH*4;
|
||||
i2sBufDesc[x].blocksize=LINE_BUFFER_LENGTH*4;
|
||||
i2sBufDesc[x].next_link_ptr=(int)((x<(PAL_LINES-1)) ? (&i2sBufDesc[x+1]) : (&i2sBufDesc[0]));
|
||||
|
||||
if (*pal_line <= x + 1)
|
||||
pal_line += 3;
|
||||
|
||||
i2sBufDesc[x].buf_ptr = (uint32_t)&i2s_dma_buffer[(*(pal_line + 1))*LINE_BUFFER_LENGTH];
|
||||
i2sBufDesc[x].unused = *(pal_line + 2);
|
||||
|
||||
}
|
||||
|
||||
i2sBufDesc[55].unused = 2;
|
||||
i2sBufDesc[367].unused = 3;
|
||||
|
||||
|
||||
/* I2S DMA initialization code */
|
||||
|
||||
//Reset DMA
|
||||
SET_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);
|
||||
CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST|SLC_TXLINK_RST);
|
||||
|
||||
//Clear DMA int flags
|
||||
SET_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
|
||||
CLEAR_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
|
||||
|
||||
//Enable and configure DMA
|
||||
CLEAR_PERI_REG_MASK(SLC_CONF0, (SLC_MODE<<SLC_MODE_S));
|
||||
SET_PERI_REG_MASK(SLC_CONF0,(1<<SLC_MODE_S));
|
||||
SET_PERI_REG_MASK(SLC_RX_DSCR_CONF,SLC_INFOR_NO_REPLACE|SLC_TOKEN_NO_REPLACE);
|
||||
CLEAR_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_FILL_EN|SLC_RX_EOF_MODE | SLC_RX_FILL_MODE);
|
||||
|
||||
CLEAR_PERI_REG_MASK(SLC_TX_LINK,SLC_TXLINK_DESCADDR_MASK);
|
||||
SET_PERI_REG_MASK(SLC_TX_LINK, ((uint32)&i2sBufDesc[1]) & SLC_TXLINK_DESCADDR_MASK); //any random desc is OK, we don't use TX but it needs something valid
|
||||
|
||||
CLEAR_PERI_REG_MASK(SLC_RX_LINK,SLC_RXLINK_DESCADDR_MASK);
|
||||
SET_PERI_REG_MASK(SLC_RX_LINK, ((uint32)&i2sBufDesc[0]) & SLC_RXLINK_DESCADDR_MASK);
|
||||
|
||||
//Attach the DMA interrupt
|
||||
ets_isr_attach(ETS_SLC_INUM, slc_isr);
|
||||
//Enable DMA operation intr
|
||||
WRITE_PERI_REG(SLC_INT_ENA, SLC_RX_EOF_INT_ENA);
|
||||
//clear any interrupt flags that are set
|
||||
WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
|
||||
///enable DMA intr in cpu
|
||||
ets_isr_unmask(1<<ETS_SLC_INUM);
|
||||
|
||||
//Start transmission
|
||||
SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START);
|
||||
SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START);
|
||||
|
||||
//Init pins to i2s functions
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_I2SO_DATA);
|
||||
|
||||
//Enable clock to i2s subsystem
|
||||
i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1);
|
||||
|
||||
//Reset I2S subsystem
|
||||
CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
|
||||
SET_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
|
||||
CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
|
||||
|
||||
//Select 16bits per channel (FIFO_MOD=0), no DMA access (FIFO only)
|
||||
CLEAR_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN|(I2S_I2S_RX_FIFO_MOD<<I2S_I2S_RX_FIFO_MOD_S)|(I2S_I2S_TX_FIFO_MOD<<I2S_I2S_TX_FIFO_MOD_S));
|
||||
|
||||
//Enable DMA in i2s subsystem
|
||||
SET_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN);
|
||||
|
||||
//tx/rx binaureal
|
||||
CLEAR_PERI_REG_MASK(I2SCONF_CHAN, (I2S_TX_CHAN_MOD<<I2S_TX_CHAN_MOD_S)|(I2S_RX_CHAN_MOD<<I2S_RX_CHAN_MOD_S));
|
||||
|
||||
//Clear int
|
||||
SET_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
|
||||
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
|
||||
CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
|
||||
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
|
||||
|
||||
//trans master&rece slave,MSB shift,right_first,msb right
|
||||
CLEAR_PERI_REG_MASK(I2SCONF, I2S_TRANS_SLAVE_MOD|(I2S_BITS_MOD<<I2S_BITS_MOD_S)|(I2S_BCK_DIV_NUM <<I2S_BCK_DIV_NUM_S)|
|
||||
(I2S_CLKM_DIV_NUM<<I2S_CLKM_DIV_NUM_S));
|
||||
|
||||
SET_PERI_REG_MASK(I2SCONF, I2S_RIGHT_FIRST|I2S_MSB_RIGHT|I2S_RECE_SLAVE_MOD|I2S_RECE_MSB_SHIFT|I2S_TRANS_MSB_SHIFT|
|
||||
((WS_I2S_BCK&I2S_BCK_DIV_NUM )<<I2S_BCK_DIV_NUM_S)|((WS_I2S_DIV&I2S_CLKM_DIV_NUM)<<I2S_CLKM_DIV_NUM_S));
|
||||
|
||||
//No idea if ints are needed...
|
||||
SET_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
|
||||
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
|
||||
CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_TX_REMPTY_INT_CLR|I2S_I2S_TX_WFULL_INT_CLR|
|
||||
I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
|
||||
//enable int
|
||||
SET_PERI_REG_MASK(I2SINT_ENA, I2S_I2S_TX_REMPTY_INT_ENA|I2S_I2S_TX_WFULL_INT_ENA|
|
||||
I2S_I2S_RX_REMPTY_INT_ENA|I2S_I2S_TX_PUT_DATA_INT_ENA|I2S_I2S_RX_TAKE_DATA_INT_ENA);
|
||||
|
||||
//Start transmission
|
||||
SET_PERI_REG_MASK(I2SCONF,I2S_I2S_TX_START);
|
||||
}
|
||||
|
||||
|
||||
#define BASEFREQ (160000000L)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,281 @@
|
|||
//Generated at 2012-10-23 19:55:03
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SLC_REGISTER_H_
|
||||
#define SLC_REGISTER_H_
|
||||
|
||||
#define REG_SLC_BASE 0x60000B00
|
||||
//version value:32'h091700
|
||||
|
||||
#define SLC_CONF0 (REG_SLC_BASE + 0x0)
|
||||
#ifndef ESP_MAC_5
|
||||
#define SLC_MODE 0x00000003
|
||||
#define SLC_MODE_S 12
|
||||
#endif
|
||||
#define SLC_DATA_BURST_EN (BIT(9))
|
||||
#define SLC_DSCR_BURST_EN (BIT(8))
|
||||
#define SLC_RX_NO_RESTART_CLR (BIT(7))
|
||||
#define SLC_RX_AUTO_WRBACK (BIT(6))
|
||||
#define SLC_RX_LOOP_TEST (BIT(5))
|
||||
#define SLC_TX_LOOP_TEST (BIT(4))
|
||||
#define SLC_AHBM_RST (BIT(3))
|
||||
#define SLC_AHBM_FIFO_RST (BIT(2))
|
||||
#define SLC_RXLINK_RST (BIT(1))
|
||||
#define SLC_TXLINK_RST (BIT(0))
|
||||
|
||||
#define SLC_INT_RAW (REG_SLC_BASE + 0x4)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_RAW (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_RAW (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_RAW (BIT(19))
|
||||
#define SLC_TOHOST_INT_RAW (BIT(18))
|
||||
#define SLC_RX_EOF_INT_RAW (BIT(17))
|
||||
#define SLC_RX_DONE_INT_RAW (BIT(16))
|
||||
#define SLC_TX_EOF_INT_RAW (BIT(15))
|
||||
#define SLC_TX_DONE_INT_RAW (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_RAW (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_RAW (BIT(12))
|
||||
#define SLC_TX_OVF_INT_RAW (BIT(11))
|
||||
#define SLC_RX_UDF_INT_RAW (BIT(10))
|
||||
#define SLC_TX_START_INT_RAW (BIT(9))
|
||||
#define SLC_RX_START_INT_RAW (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_RAW (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_RAW (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_RAW (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_RAW (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_RAW (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_RAW (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_RAW (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_RAW (BIT(0))
|
||||
|
||||
#define SLC_INT_STATUS (REG_SLC_BASE + 0x8)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_ST (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_ST (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_ST (BIT(19))
|
||||
#define SLC_TOHOST_INT_ST (BIT(18))
|
||||
#define SLC_RX_EOF_INT_ST (BIT(17))
|
||||
#define SLC_RX_DONE_INT_ST (BIT(16))
|
||||
#define SLC_TX_EOF_INT_ST (BIT(15))
|
||||
#define SLC_TX_DONE_INT_ST (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_ST (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_ST (BIT(12))
|
||||
#define SLC_TX_OVF_INT_ST (BIT(11))
|
||||
#define SLC_RX_UDF_INT_ST (BIT(10))
|
||||
#define SLC_TX_START_INT_ST (BIT(9))
|
||||
#define SLC_RX_START_INT_ST (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_ST (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_ST (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_ST (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_ST (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_ST (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_ST (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_ST (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_ST (BIT(0))
|
||||
|
||||
#define SLC_INT_ENA (REG_SLC_BASE + 0xC)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_ENA (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_ENA (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_ENA (BIT(19))
|
||||
#define SLC_TOHOST_INT_ENA (BIT(18))
|
||||
#define SLC_RX_EOF_INT_ENA (BIT(17))
|
||||
#define SLC_RX_DONE_INT_ENA (BIT(16))
|
||||
#define SLC_TX_EOF_INT_ENA (BIT(15))
|
||||
#define SLC_TX_DONE_INT_ENA (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_ENA (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_ENA (BIT(12))
|
||||
#define SLC_TX_OVF_INT_ENA (BIT(11))
|
||||
#define SLC_RX_UDF_INT_ENA (BIT(10))
|
||||
#define SLC_TX_START_INT_ENA (BIT(9))
|
||||
#define SLC_RX_START_INT_ENA (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_ENA (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_ENA (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_ENA (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_ENA (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_ENA (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_ENA (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_ENA (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_ENA (BIT(0))
|
||||
|
||||
#define SLC_FRHOST_BIT_INT_ENA_ALL 0xff
|
||||
|
||||
#define SLC_INT_CLR (REG_SLC_BASE + 0x10)
|
||||
#define SLC_TX_DSCR_EMPTY_INT_CLR (BIT(21))
|
||||
#define SLC_RX_DSCR_ERR_INT_CLR (BIT(20))
|
||||
#define SLC_TX_DSCR_ERR_INT_CLR (BIT(19))
|
||||
#define SLC_TOHOST_INT_CLR (BIT(18))
|
||||
#define SLC_RX_EOF_INT_CLR (BIT(17))
|
||||
#define SLC_RX_DONE_INT_CLR (BIT(16))
|
||||
#define SLC_TX_EOF_INT_CLR (BIT(15))
|
||||
#define SLC_TX_DONE_INT_CLR (BIT(14))
|
||||
#define SLC_TOKEN1_1TO0_INT_CLR (BIT(13))
|
||||
#define SLC_TOKEN0_1TO0_INT_CLR (BIT(12))
|
||||
#define SLC_TX_OVF_INT_CLR (BIT(11))
|
||||
#define SLC_RX_UDF_INT_CLR (BIT(10))
|
||||
#define SLC_TX_START_INT_CLR (BIT(9))
|
||||
#define SLC_RX_START_INT_CLR (BIT(8))
|
||||
#define SLC_FRHOST_BIT7_INT_CLR (BIT(7))
|
||||
#define SLC_FRHOST_BIT6_INT_CLR (BIT(6))
|
||||
#define SLC_FRHOST_BIT5_INT_CLR (BIT(5))
|
||||
#define SLC_FRHOST_BIT4_INT_CLR (BIT(4))
|
||||
#define SLC_FRHOST_BIT3_INT_CLR (BIT(3))
|
||||
#define SLC_FRHOST_BIT2_INT_CLR (BIT(2))
|
||||
#define SLC_FRHOST_BIT1_INT_CLR (BIT(1))
|
||||
#define SLC_FRHOST_BIT0_INT_CLR (BIT(0))
|
||||
|
||||
#define SLC_RX_STATUS (REG_SLC_BASE + 0x14)
|
||||
#define SLC_RX_EMPTY (BIT(1))
|
||||
#define SLC_RX_FULL (BIT(0))
|
||||
|
||||
#define SLC_RX_FIFO_PUSH (REG_SLC_BASE + 0x18)
|
||||
#define SLC_RXFIFO_PUSH (BIT(16))
|
||||
#define SLC_RXFIFO_WDATA 0x000001FF
|
||||
#define SLC_RXFIFO_WDATA_S 0
|
||||
|
||||
#define SLC_TX_STATUS (REG_SLC_BASE + 0x1C)
|
||||
#define SLC_TX_EMPTY (BIT(1))
|
||||
#define SLC_TX_FULL (BIT(0))
|
||||
|
||||
#define SLC_TX_FIFO_POP (REG_SLC_BASE + 0x20)
|
||||
#define SLC_TXFIFO_POP (BIT(16))
|
||||
#define SLC_TXFIFO_RDATA 0x000007FF
|
||||
#define SLC_TXFIFO_RDATA_S 0
|
||||
|
||||
#define SLC_RX_LINK (REG_SLC_BASE + 0x24)
|
||||
#define SLC_RXLINK_PARK (BIT(31))
|
||||
#define SLC_RXLINK_RESTART (BIT(30))
|
||||
#define SLC_RXLINK_START (BIT(29))
|
||||
#define SLC_RXLINK_STOP (BIT(28))
|
||||
#define SLC_RXLINK_DESCADDR_MASK 0x000FFFFF
|
||||
#define SLC_RXLINK_ADDR_S 0
|
||||
|
||||
#define SLC_TX_LINK (REG_SLC_BASE + 0x28)
|
||||
#define SLC_TXLINK_PARK (BIT(31))
|
||||
#define SLC_TXLINK_RESTART (BIT(30))
|
||||
#define SLC_TXLINK_START (BIT(29))
|
||||
#define SLC_TXLINK_STOP (BIT(28))
|
||||
#define SLC_TXLINK_DESCADDR_MASK 0x000FFFFF
|
||||
#define SLC_TXLINK_ADDR_S 0
|
||||
|
||||
#define SLC_INTVEC_TOHOST (REG_SLC_BASE + 0x2C)
|
||||
#define SLC_TOHOST_INTVEC 0x000000FF
|
||||
#define SLC_TOHOST_INTVEC_S 0
|
||||
|
||||
#define SLC_TOKEN0 (REG_SLC_BASE + 0x30)
|
||||
#define SLC_TOKEN0_MASK 0x00000FFF
|
||||
#define SLC_TOKEN0_S 16
|
||||
#define SLC_TOKEN0_LOCAL_INC_MORE (BIT(14))
|
||||
#define SLC_TOKEN0_LOCAL_INC (BIT(13))
|
||||
#define SLC_TOKEN0_LOCAL_WR (BIT(12))
|
||||
#define SLC_TOKEN0_LOCAL_WDATA_MASK 0x00000FFF
|
||||
#define SLC_TOKEN0_LOCAL_WDATA_S 0
|
||||
|
||||
#define SLC_TOKEN1 (REG_SLC_BASE + 0x34)
|
||||
#define SLC_TOKEN1_MASK 0x00000FFF
|
||||
#define SLC_TOKEN1_S 16
|
||||
#define SLC_TOKEN1_LOCAL_INC_MORE (BIT(14))
|
||||
#define SLC_TOKEN1_LOCAL_INC (BIT(13))
|
||||
#define SLC_TOKEN1_LOCAL_WR (BIT(12))
|
||||
#define SLC_TOKEN1_LOCAL_WDATA 0x00000FFF
|
||||
#define SLC_TOKEN1_LOCAL_WDATA_S 0
|
||||
|
||||
#define SLC_CONF1 (REG_SLC_BASE + 0x38)
|
||||
#define SLC_STATE0 (REG_SLC_BASE + 0x3C)
|
||||
#define SLC_STATE1 (REG_SLC_BASE + 0x40)
|
||||
|
||||
#define SLC_BRIDGE_CONF (REG_SLC_BASE + 0x44)
|
||||
#ifndef ESP_MAC_5
|
||||
#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF
|
||||
#define SLC_TX_PUSH_IDLE_NUM_S 16
|
||||
#define SLC_TX_DUMMY_MODE (BIT(12))
|
||||
#endif
|
||||
#define SLC_FIFO_MAP_ENA 0x0000000F
|
||||
#define SLC_FIFO_MAP_ENA_S 8
|
||||
#define SLC_TXEOF_ENA 0x0000003F
|
||||
#define SLC_TXEOF_ENA_S 0
|
||||
|
||||
#define SLC_RX_EOF_DES_ADDR (REG_SLC_BASE + 0x48)
|
||||
#define SLC_TX_EOF_DES_ADDR (REG_SLC_BASE + 0x4C)
|
||||
#define SLC_FROM_HOST_LAST_DESC SLC_TX_EOF_DES_ADDR
|
||||
#define SLC_TO_HOST_LAST_DESC SLC_RX_EOF_DES_ADDR
|
||||
|
||||
#define SLC_RX_EOF_BFR_DES_ADDR (REG_SLC_BASE + 0x50)
|
||||
#define SLC_AHB_TEST (REG_SLC_BASE + 0x54)
|
||||
#define SLC_AHB_TESTADDR 0x00000003
|
||||
#define SLC_AHB_TESTADDR_S 4
|
||||
#define SLC_AHB_TESTMODE 0x00000007
|
||||
#define SLC_AHB_TESTMODE_S 0
|
||||
|
||||
#define SLC_SDIO_ST (REG_SLC_BASE + 0x58)
|
||||
#define SLC_BUS_ST 0x00000007
|
||||
#define SLC_BUS_ST_S 12
|
||||
#define SLC_SDIO_WAKEUP (BIT(8))
|
||||
#define SLC_FUNC_ST 0x0000000F
|
||||
#define SLC_FUNC_ST_S 4
|
||||
#define SLC_CMD_ST 0x00000007
|
||||
#define SLC_CMD_ST_S 0
|
||||
|
||||
#define SLC_RX_DSCR_CONF (REG_SLC_BASE + 0x5C)
|
||||
#ifdef ESP_MAC_5
|
||||
#define SLC_INFOR_NO_REPLACE (BIT(9))
|
||||
#define SLC_TOKEN_NO_REPLACE (BIT(8))
|
||||
#define SLC_POP_IDLE_CNT 0x000000FF
|
||||
#else
|
||||
#define SLC_RX_FILL_EN (BIT(20))
|
||||
#define SLC_RX_EOF_MODE (BIT(19))
|
||||
#define SLC_RX_FILL_MODE (BIT(18))
|
||||
#define SLC_INFOR_NO_REPLACE (BIT(17))
|
||||
#define SLC_TOKEN_NO_REPLACE (BIT(16))
|
||||
#define SLC_POP_IDLE_CNT 0x0000FFFF
|
||||
#endif
|
||||
#define SLC_POP_IDLE_CNT_S 0
|
||||
|
||||
#define SLC_TXLINK_DSCR (REG_SLC_BASE + 0x60)
|
||||
#define SLC_TXLINK_DSCR_BF0 (REG_SLC_BASE + 0x64)
|
||||
#define SLC_TXLINK_DSCR_BF1 (REG_SLC_BASE + 0x68)
|
||||
#define SLC_RXLINK_DSCR (REG_SLC_BASE + 0x6C)
|
||||
#define SLC_RXLINK_DSCR_BF0 (REG_SLC_BASE + 0x70)
|
||||
#define SLC_RXLINK_DSCR_BF1 (REG_SLC_BASE + 0x74)
|
||||
#define SLC_DATE (REG_SLC_BASE + 0x78)
|
||||
#define SLC_ID (REG_SLC_BASE + 0x7C)
|
||||
|
||||
#define SLC_HOST_CONF_W0 (REG_SLC_BASE + 0x80 + 0x14)
|
||||
#define SLC_HOST_CONF_W1 (REG_SLC_BASE + 0x80 + 0x18)
|
||||
#define SLC_HOST_CONF_W2 (REG_SLC_BASE + 0x80 + 0x20)
|
||||
#define SLC_HOST_CONF_W3 (REG_SLC_BASE + 0x80 + 0x24)
|
||||
#define SLC_HOST_CONF_W4 (REG_SLC_BASE + 0x80 + 0x28)
|
||||
|
||||
#define SLC_HOST_INTR_ST (REG_SLC_BASE + 0x80 + 0x1c)
|
||||
#define SLC_HOST_INTR_CLR (REG_SLC_BASE + 0x80 + 0x30)
|
||||
#define SLC_HOST_INTR_SOF_BIT (BIT(12))
|
||||
|
||||
#define SLC_HOST_INTR_ENA (REG_SLC_BASE + 0x80 + 0x34)
|
||||
#define SLC_RX_NEW_PACKET_INT_ENA (BIT23)
|
||||
#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT0)
|
||||
#define SLC_HOST_CONF_W5 (REG_SLC_BASE + 0x80 + 0x3C)
|
||||
#define SLC_HOST_INTR_RAW (REG_SLC_BASE + 0x80 + 0x8)
|
||||
#define SLC_HOST_INTR_ENA_BIT (BIT(23))
|
||||
//[15:12]: 0x3ff9xxxx -- 0b01 from_host
|
||||
// 0x3ffaxxxx -- 0b10 general
|
||||
// 0x3ffbxxxx -- 0b11 to_host
|
||||
#define SLC_DATA_ADDR_CLEAR_MASK (~(0xf<<12))
|
||||
#define SLC_FROM_HOST_ADDR_MASK (0x1<<12)
|
||||
#define SLC_TO_HOST_ADDR_MASK (0x3<<12)
|
||||
|
||||
#define SLC_SET_FROM_HOST_ADDR_MASK(v) do { \
|
||||
(v) &= SLC_DATA_ADDR_CLEAR_MASK; \
|
||||
(v) |= SLC_FROM_HOST_ADDR_MASK; \
|
||||
} while(0);
|
||||
|
||||
#define SLC_SET_TO_HOST_ADDR_MASK(v) do { \
|
||||
(v) &= SLC_DATA_ADDR_CLEAR_MASK; \
|
||||
(v) |= SLC_TO_HOST_ADDR_MASK; \
|
||||
} while(0);
|
||||
|
||||
|
||||
#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c //[15:0] set to 0xcccc
|
||||
|
||||
|
||||
#endif // SLC_REGISTER_H_INCLUDED
|
||||
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
#include "c_types.h"
|
||||
#include "mem.h"
|
||||
#include "user_interface.h"
|
||||
#include "ets_sys.h"
|
||||
#include "osapi.h"
|
||||
#include "espconn.h"
|
||||
#include "woz_monitor.h"
|
||||
#include "spi_flash.h"
|
||||
#include <ip_addr.h>
|
||||
|
||||
#define RAM_SIZE 0x5000
|
||||
#define INSTRUCTIONS_CHUNK 10000
|
||||
|
||||
#define TERM_WIDTH 40
|
||||
#define TERM_HEIGHT 24
|
||||
|
||||
#define SPACE 0x20
|
||||
|
||||
|
||||
static volatile os_timer_t emulator_callback_timer, cursor_timer;
|
||||
|
||||
uint8_t computer_ram[RAM_SIZE],
|
||||
terminal_ram[TERM_WIDTH * TERM_HEIGHT];
|
||||
|
||||
uint16_t load_target_start;
|
||||
|
||||
uint32_t current_start,
|
||||
current_end,
|
||||
loop_counter = 0;
|
||||
|
||||
/* Current terminal row and column */
|
||||
uint8_t term_x = 0,
|
||||
term_y = 0,
|
||||
cursor_visible = 0,
|
||||
cursor_disabled = 0;
|
||||
|
||||
struct pia6821 {
|
||||
uint8_t keyboard_register;
|
||||
uint8_t keyboard_control;
|
||||
uint8_t display_register;
|
||||
uint8_t display_control;
|
||||
|
||||
} pia = {0};
|
||||
|
||||
|
||||
/* ---------- Function definitions ------------ */
|
||||
|
||||
void ICACHE_FLASH_ATTR reset_emulator() {
|
||||
term_x = 0;
|
||||
term_y = 0;
|
||||
|
||||
ets_memset( computer_ram, 0xff, sizeof(computer_ram) );
|
||||
ets_memset( terminal_ram, 0b100000, sizeof(terminal_ram) );
|
||||
reset6502();
|
||||
}
|
||||
|
||||
uint8_t read6502(uint16_t address) {
|
||||
/* Address in RAM */
|
||||
if (address < RAM_SIZE)
|
||||
return computer_ram[address];
|
||||
|
||||
/* 4kB of RAM (0x4000-0x5000) is logically mapped to memory bank 0xE000, needed for BASIC. */
|
||||
else if ((address & 0xF000) == 0xE000)
|
||||
return computer_ram[address - 0xA000];
|
||||
|
||||
/* PIA peripheral interface */
|
||||
else if ((address & 0xFFF0) == 0xD010) {
|
||||
/* Set keyboard control register to 0 if key was read */
|
||||
if (address == 0xD010) {
|
||||
pia.keyboard_control = 0x00;
|
||||
}
|
||||
|
||||
return *(&pia.keyboard_register + address - 0xD010);
|
||||
}
|
||||
|
||||
/* Address belongs to Woz Monitor ROM (0xFF00 - 0xFFFF) */
|
||||
else if ((address & 0xFF00) == 0xFF00)
|
||||
return woz_monitor[address - 0xFF00];
|
||||
|
||||
/* Default value */
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
|
||||
void ICACHE_FLASH_ATTR toggle_cursor() {
|
||||
uint8_t i;
|
||||
|
||||
cursor_visible ^= 1;
|
||||
terminal_ram[term_y * TERM_WIDTH + term_x] = cursor_visible | cursor_disabled ? 0x20 : 0x00;
|
||||
}
|
||||
|
||||
|
||||
void ICACHE_FLASH_ATTR terminal_write(uint8_t value) {
|
||||
/* When changing the terminal_ram, disable cursor first */
|
||||
cursor_disabled = 1;
|
||||
|
||||
/* Commit change */
|
||||
toggle_cursor();
|
||||
|
||||
/* End of line reached or return pressed */
|
||||
if(term_x > 39 || value == 0x0D) {
|
||||
term_x = 0;
|
||||
|
||||
if(term_y >= 23) {
|
||||
/* Scroll 1 line up (copy 23 text lines only, blank the last one) */
|
||||
ets_memcpy(terminal_ram, &terminal_ram[TERM_WIDTH], TERM_WIDTH * (TERM_HEIGHT - 1));
|
||||
ets_memset(terminal_ram + TERM_WIDTH * (TERM_HEIGHT - 1), SPACE, TERM_WIDTH);
|
||||
|
||||
}
|
||||
else
|
||||
term_y++;
|
||||
|
||||
}
|
||||
|
||||
/* Only printable characters go to terminal RAM. Other characters don't move the cursor either. */
|
||||
if (value >= 0x20 && value <= 0x7E) {
|
||||
terminal_ram[term_y * TERM_WIDTH + term_x] = value & 0x3F;
|
||||
term_x++;
|
||||
}
|
||||
|
||||
/* Enable cursor again */
|
||||
cursor_disabled = 0;
|
||||
}
|
||||
|
||||
|
||||
void write6502(uint16_t address, uint8_t value)
|
||||
{
|
||||
if(address < RAM_SIZE) {
|
||||
computer_ram[address] = value;
|
||||
}
|
||||
|
||||
/* Address belongs to a 4kB bank mapped at (0xE000 - 0xF000), translate it to real RAM 0x4000-0x5000
|
||||
* this is needed to run Apple BASIC */
|
||||
else if((address & 0xF000) == 0xE000) {
|
||||
computer_ram[address - 0xA000] = value;
|
||||
}
|
||||
|
||||
/* Write to PIA chip. */
|
||||
else if (address == 0xD010) {
|
||||
pia.keyboard_register = value;
|
||||
|
||||
/* If a key was pressed, write to keyboard control register as well */
|
||||
pia.keyboard_control = 0xFF;
|
||||
}
|
||||
else if (address == 0xD012) {
|
||||
terminal_write(value ^ 0x80);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void ICACHE_FLASH_ATTR emulator_task(os_event_t *events)
|
||||
{
|
||||
current_start = system_get_time();
|
||||
exec6502(INSTRUCTIONS_CHUNK);
|
||||
current_end = system_get_time();
|
||||
}
|
||||
|
||||
|
||||
static void ICACHE_FLASH_ATTR dataRecvCallback(void *arg, char *pusrdata, unsigned short lenght){
|
||||
|
||||
char input_character = *pusrdata;
|
||||
|
||||
/* Convert lowercase to uppercase */
|
||||
if (input_character > 0x60 && input_character < 0x7B)
|
||||
input_character ^= 0x20;
|
||||
|
||||
/* Convert LF to CR */
|
||||
else if (input_character == 0x0A)
|
||||
input_character = 0x0D;
|
||||
|
||||
/* Convert backspace to "rub out" */
|
||||
else if (input_character == 0x7F)
|
||||
input_character = '_';
|
||||
|
||||
/* Enable CPU reset from telnet (Ctrl + C) */
|
||||
else if (input_character == 0x03) {
|
||||
reset_emulator();
|
||||
return;
|
||||
}
|
||||
|
||||
write6502(0xd010, input_character | 0x80);
|
||||
}
|
||||
|
||||
|
||||
static void ICACHE_FLASH_ATTR connectionCallback(void *arg){
|
||||
struct espconn *telnet_server = arg;
|
||||
espconn_regist_recvcb(telnet_server, dataRecvCallback);
|
||||
}
|
||||
|
||||
|
||||
void tftp_server_recv(void *arg, char *pdata, unsigned short len)
|
||||
{
|
||||
struct espconn* udp_server_local = arg;
|
||||
uint8_t ack[] = {0x00, 0x04, 0x00, 0x00};
|
||||
|
||||
if (len < 4)
|
||||
return;
|
||||
|
||||
/* Write request, this is the first package */
|
||||
if (pdata[1] == 0x02) {
|
||||
load_target_start = (computer_ram[0x27] << 8) + computer_ram[0x26];
|
||||
if (load_target_start >= 0xE000)
|
||||
load_target_start -= 0xA000;
|
||||
}
|
||||
|
||||
/* Data packet */
|
||||
else if(pdata[1] == 0x03) {
|
||||
/* Copy sequence number into ACK packet and send it */
|
||||
ets_memcpy(&ack[2], &pdata[2], 2);
|
||||
|
||||
ets_memcpy(&computer_ram[load_target_start], pdata + 4, len - 4);
|
||||
load_target_start += (len - 4);
|
||||
|
||||
}
|
||||
|
||||
espconn_send(udp_server_local, ack, 4);
|
||||
}
|
||||
|
||||
|
||||
void ICACHE_FLASH_ATTR user_init(void)
|
||||
{
|
||||
uint16_t ui_address;
|
||||
struct ip_info ip_address;
|
||||
|
||||
char ssid[32] = "SSID";
|
||||
char password[32] = "PASSWORD";
|
||||
|
||||
uart_div_modify(0, UART_CLK_FREQ / 115200);
|
||||
|
||||
uint32 credentials[16] = {0};
|
||||
|
||||
spi_flash_read(0x3c000, (uint32 *)&credentials[0], 16 * sizeof(uint32));
|
||||
|
||||
struct station_config stationConf;
|
||||
|
||||
ets_strcpy(&stationConf.ssid, &credentials[0]);
|
||||
ets_strcpy(&stationConf.password, &credentials[8]);
|
||||
|
||||
current_start = system_get_time();
|
||||
|
||||
reset_emulator();
|
||||
testi2s_init();
|
||||
|
||||
system_update_cpu_freq( SYS_CPU_160MHZ );
|
||||
|
||||
/* Create a 10ms timer to call back the emulator task function periodically */
|
||||
os_timer_setfn(&emulator_callback_timer, (os_timer_func_t *) emulator_task, NULL);
|
||||
os_timer_arm(&emulator_callback_timer, 10, 1);
|
||||
|
||||
/* Toggle cursor every 300 ms */
|
||||
os_timer_setfn(&cursor_timer, (os_timer_func_t *) toggle_cursor, NULL);
|
||||
os_timer_arm(&cursor_timer, 300, 1);
|
||||
|
||||
/* Initialize wifi connection */
|
||||
wifi_set_opmode( STATION_MODE );
|
||||
|
||||
wifi_station_set_config(&stationConf);
|
||||
wifi_set_phy_mode(PHY_MODE_11B);
|
||||
wifi_station_set_auto_connect(1);
|
||||
wifi_station_connect();
|
||||
|
||||
|
||||
/* TFTP server */
|
||||
struct espconn *tftp_server = (struct espconn *)os_zalloc(sizeof(struct espconn));
|
||||
ets_memset( tftp_server, 0, sizeof( struct espconn ) );
|
||||
tftp_server->type = ESPCONN_UDP;
|
||||
tftp_server->proto.udp = (esp_udp *)os_zalloc(sizeof(esp_udp));
|
||||
tftp_server->proto.udp->local_port = 69;
|
||||
|
||||
espconn_regist_recvcb(tftp_server, tftp_server_recv);
|
||||
espconn_create(tftp_server);
|
||||
|
||||
|
||||
/* Telnet server */
|
||||
struct espconn *telnet_server = (struct espconn *)os_zalloc(sizeof(struct espconn));
|
||||
ets_memset(telnet_server, 0, sizeof(struct espconn));
|
||||
|
||||
espconn_create(telnet_server);
|
||||
telnet_server->type = ESPCONN_TCP;
|
||||
telnet_server->proto.tcp = (esp_tcp *)os_zalloc(sizeof(esp_tcp));
|
||||
telnet_server->proto.tcp->local_port = 23;
|
||||
espconn_regist_connectcb(telnet_server, connectionCallback);
|
||||
|
||||
espconn_accept(telnet_server);
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
uint8_t woz_monitor[] = {
|
||||
0xD8, 0x58, 0xA0, 0x7F, 0x8C, 0x12, 0xD0, 0xA9,
|
||||
0xA7, 0x8D, 0x11, 0xD0, 0x8D, 0x13, 0xD0, 0xC9,
|
||||
0xDF, 0xF0, 0x13, 0xC9, 0x9B, 0xF0, 0x03, 0xC8,
|
||||
0x10, 0x0F, 0xA9, 0xDC, 0x20, 0xEF, 0xFF, 0xA9,
|
||||
0x8D, 0x20, 0xEF, 0xFF, 0xA0, 0x01, 0x88, 0x30,
|
||||
0xF6, 0xAD, 0x11, 0xD0, 0x10, 0xFB, 0xAD, 0x10,
|
||||
0xD0, 0x99, 0x00, 0x02, 0x20, 0xEF, 0xFF, 0xC9,
|
||||
0x8D, 0xD0, 0xD4, 0xA0, 0xFF, 0xA9, 0x00, 0xAA,
|
||||
0x0A, 0x85, 0x2B, 0xC8, 0xB9, 0x00, 0x02, 0xC9,
|
||||
0x8D, 0xF0, 0xD4, 0xC9, 0xAE, 0x90, 0xF4, 0xF0,
|
||||
0xF0, 0xC9, 0xBA, 0xF0, 0xEB, 0xC9, 0xD2, 0xF0,
|
||||
0x3B, 0x86, 0x28, 0x86, 0x29, 0x84, 0x2A, 0xB9,
|
||||
0x00, 0x02, 0x49, 0xB0, 0xC9, 0x0A, 0x90, 0x06,
|
||||
0x69, 0x88, 0xC9, 0xFA, 0x90, 0x11, 0x0A, 0x0A,
|
||||
0x0A, 0x0A, 0xA2, 0x04, 0x0A, 0x26, 0x28, 0x26,
|
||||
0x29, 0xCA, 0xD0, 0xF8, 0xC8, 0xD0, 0xE0, 0xC4,
|
||||
0x2A, 0xF0, 0x97, 0x24, 0x2B, 0x50, 0x10, 0xA5,
|
||||
0x28, 0x81, 0x26, 0xE6, 0x26, 0xD0, 0xB5, 0xE6,
|
||||
0x27, 0x4C, 0x44, 0xFF, 0x6C, 0x24, 0x00, 0x30,
|
||||
0x2B, 0xA2, 0x02, 0xB5, 0x27, 0x95, 0x25, 0x95,
|
||||
0x23, 0xCA, 0xD0, 0xF7, 0xD0, 0x14, 0xA9, 0x8D,
|
||||
0x20, 0xEF, 0xFF, 0xA5, 0x25, 0x20, 0xDC, 0xFF,
|
||||
0xA5, 0x24, 0x20, 0xDC, 0xFF, 0xA9, 0xBA, 0x20,
|
||||
0xEF, 0xFF, 0xA9, 0xA0, 0x20, 0xEF, 0xFF, 0xA1,
|
||||
0x24, 0x20, 0xDC, 0xFF, 0x86, 0x2B, 0xA5, 0x24,
|
||||
0xC5, 0x28, 0xA5, 0x25, 0xE5, 0x29, 0xB0, 0xC1,
|
||||
0xE6, 0x24, 0xD0, 0x02, 0xE6, 0x25, 0xA5, 0x24,
|
||||
0x29, 0x07, 0x10, 0xC8, 0x48, 0x4A, 0x4A, 0x4A,
|
||||
0x4A, 0x20, 0xE5, 0xFF, 0x68, 0x29, 0x0F, 0x09,
|
||||
0xB0, 0xC9, 0xBA, 0x90, 0x02, 0x69, 0x06, 0x2C,
|
||||
0x12, 0xD0, 0x30, 0xFB, 0x8D, 0x12, 0xD0, 0x60,
|
||||
0x00, 0x00, 0x00, 0x0F, 0x00, 0xFF, 0x00, 0x00
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue