70 lines
2.1 KiB
Verilog
70 lines
2.1 KiB
Verilog
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`ifndef HVSYNC_GENERATOR_H
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`define HVSYNC_GENERATOR_H
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/*
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Video sync generator, used to drive a simulated CRT.
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To use:
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- Wire the hsync and vsync signals to top level outputs
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- Add a 3-bit (or more) "rgb" output to the top level
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*/
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module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
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input clk;
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input reset;
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output reg hsync, vsync;
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output display_on;
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output reg [8:0] hpos;
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output reg [8:0] vpos;
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// declarations for TV-simulator sync parameters
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// horizontal constants
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parameter H_DISPLAY = 256; // horizontal display width
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parameter H_BACK = 23; // horizontal left border (back porch)
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parameter H_FRONT = 7; // horizontal right border (front porch)
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parameter H_SYNC = 23; // horizontal sync width
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// vertical constants
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parameter V_DISPLAY = 240; // vertical display height
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parameter V_TOP = 5; // vertical top border
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parameter V_BOTTOM = 14; // vertical bottom border
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parameter V_SYNC = 3; // vertical sync # lines
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// derived constants
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parameter H_SYNC_START = H_DISPLAY + H_FRONT;
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parameter H_SYNC_END = H_DISPLAY + H_FRONT + H_SYNC - 1;
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parameter H_MAX = H_DISPLAY + H_BACK + H_FRONT + H_SYNC - 1;
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parameter V_SYNC_START = V_DISPLAY + V_BOTTOM;
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parameter V_SYNC_END = V_DISPLAY + V_BOTTOM + V_SYNC - 1;
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parameter V_MAX = V_DISPLAY + V_TOP + V_BOTTOM + V_SYNC - 1;
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wire hmaxxed = (hpos == H_MAX) || reset; // set when hpos is maximum
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wire vmaxxed = (vpos == V_MAX) || reset; // set when vpos is maximum
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// horizontal position counter
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always @(posedge clk)
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begin
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hsync <= (hpos>=H_SYNC_START && hpos<=H_SYNC_END);
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if(hmaxxed)
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hpos <= 0;
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else
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hpos <= hpos + 1;
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end
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// vertical position counter
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always @(posedge clk)
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begin
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vsync <= (vpos>=V_SYNC_START && vpos<=V_SYNC_END);
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if(hmaxxed)
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if (vmaxxed)
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vpos <= 0;
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else
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vpos <= vpos + 1;
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end
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// display_on is set when beam is in "safe" visible frame
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assign display_on = (hpos<H_DISPLAY) && (vpos<V_DISPLAY);
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endmodule
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`endif
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