mirror of
https://github.com/jonthomasson/retro1.git
synced 2024-07-04 01:29:33 +00:00
485 lines
22 KiB
Plaintext
485 lines
22 KiB
Plaintext
ca65 V2.15 - Git a85ac88
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Main file : firmware.s65
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Current file: firmware.s65
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000000r 1 .setcpu "65c02"
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000000r 1 .include "macros.inc65"
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000000r 2 ; Push A and X, destroys A
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000000r 2 .macro phax
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000000r 2 pha
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000000r 2 txa
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000000r 2 pha
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push A and Y, destroys A
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000000r 2 .macro phay
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000000r 2 pha
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000000r 2 tya
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000000r 2 pha
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Push A, X and Y, destroys A
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000000r 2 .macro phaxy
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000000r 2 pha
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000000r 2 txa
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000000r 2 pha
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000000r 2 tya
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000000r 2 pha
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A and X
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000000r 2 .macro plax
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000000r 2 pla
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000000r 2 tax
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A and Y
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000000r 2 .macro play
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000000r 2 pla
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000000r 2 tay
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Pull A, X and Y
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000000r 2 .macro plaxy
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000000r 2 pla
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000000r 2 tay
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000000r 2 pla
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000000r 2 tax
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000000r 2 pla
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000000r 2 .endmacro
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000000r 2
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000000r 2 ; Load zero page register reg/reg+1 with the 16-bit value, destroys A
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000000r 2 .macro ld16 reg, value
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000000r 2 lda #<(value)
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000000r 2 sta reg
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000000r 2 lda #>(value)
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000000r 2 sta reg + 1
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000000r 2 .endmacro
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000000r 2
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000000r 1
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000000r 1 .include "io.inc65"
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000000r 2 ; CPU frequency
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000000r 2
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000000r 2 F_CPU = 1000000
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000000r 2
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000000r 2 ; ACIA registers
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000000r 2
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000000r 2 ACIA_BASE = $7f00
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000000r 2 ACIA_DATA = ACIA_BASE
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000000r 2 ACIA_STATUS = ACIA_BASE + 1
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000000r 2 ACIA_COMMAND = ACIA_BASE + 2
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000000r 2 ACIA_CONTROL = ACIA_BASE + 3
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000000r 2
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000000r 2 ; ACIA control register bit values
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000000r 2
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000000r 2 ACIA_STOP_BITS_1 = %00000000
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000000r 2 ACIA_STOP_BITS_2 = %10000000
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000000r 2 ACIA_DATA_BITS_8 = %00000000
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000000r 2 ACIA_DATA_BITS_7 = %00100000
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000000r 2 ACIA_DATA_BITS_6 = %01000000
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000000r 2 ACIA_DATA_BITS_5 = %01100000
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000000r 2 ACIA_CLOCK_EXT = %00000000
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000000r 2 ACIA_CLOCK_INT = %00010000
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000000r 2 ACIA_BAUD_16XEXT = %00000000
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000000r 2 ACIA_BAUD_50 = %00000001
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000000r 2 ACIA_BAUD_75 = %00000010
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000000r 2 ACIA_BAUD_109 = %00000011
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000000r 2 ACIA_BAUD_134 = %00000100
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000000r 2 ACIA_BAUD_150 = %00000101
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000000r 2 ACIA_BAUD_300 = %00000110
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000000r 2 ACIA_BAUD_600 = %00000111
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000000r 2 ACIA_BAUD_1200 = %00001000
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000000r 2 ACIA_BAUD_1800 = %00001001
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000000r 2 ACIA_BAUD_2400 = %00001010
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000000r 2 ACIA_BAUD_3600 = %00001011
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000000r 2 ACIA_BAUD_4800 = %00001100
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000000r 2 ACIA_BAUD_7200 = %00001101
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000000r 2 ACIA_BAUD_9600 = %00001110
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000000r 2 ACIA_BAUD_19200 = %00001111
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000000r 2
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000000r 2 ; ACIA command register bit values
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000000r 2
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000000r 2 ACIA_PARITY_ODD = %00000000
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000000r 2 ACIA_PARITY_EVEN = %01000000
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000000r 2 ACIA_PARITY_MARK = %10000000
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000000r 2 ACIA_PARITY_SPACE = %11000000
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000000r 2 ACIA_PARITY_DISABLE = %00000000
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000000r 2 ACIA_PARITY_ENABLE = %00100000
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000000r 2 ACIA_ECHO_DISABLE = %00000000
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000000r 2 ACIA_ECHO_ENABLE = %00010000
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000000r 2 ACIA_TX_INT_DISABLE_RTS_HIGH = %00000000
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000000r 2 ACIA_TX_INT_ENABLE_RTS_LOW = %00000100
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000000r 2 ACIA_TX_INT_DISABLE_RTS_LOW = %00001000
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000000r 2 ACIA_TX_INT_DISABLE_BREAK = %00001100
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000000r 2 ACIA_RX_INT_ENABLE = %00000000
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000000r 2 ACIA_RX_INT_DISABLE = %00000010
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000000r 2 ACIA_DTR_HIGH = %00000000
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000000r 2 ACIA_DTR_LOW = %00000001
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000000r 2
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000000r 2 ; ACIA status register bit masks
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000000r 2
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000000r 2 ACIA_STATUS_IRQ = 1 << 7
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000000r 2 ACIA_STATUS_DSR = 1 << 6
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000000r 2 ACIA_STATUS_DCD = 1 << 5
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000000r 2 ACIA_STATUS_TX_EMPTY = 1 << 4
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000000r 2 ACIA_STATUS_RX_FULL = 1 << 3
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000000r 2 ACIA_STATUS_OVERRUN = 1 << 2
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000000r 2 ACIA_STATUS_FRAME_ERR = 1 << 1
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000000r 2 ACIA_STATUS_PARITY_ERR = 1 << 0
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000000r 2
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000000r 2 ; VIA registers
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000000r 2
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000000r 2 VIA1_BASE = $8020
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000000r 2 VIA1_ORB = VIA1_BASE
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000000r 2 VIA1_IRB = VIA1_BASE
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000000r 2 VIA1_ORA = VIA1_BASE + 1
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000000r 2 VIA1_IRA = VIA1_BASE + 1
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000000r 2 VIA1_DDRB = VIA1_BASE + 2
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000000r 2 VIA1_DDRA = VIA1_BASE + 3
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000000r 2 VIA1_T1C_L = VIA1_BASE + 4
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000000r 2 VIA1_T1C_H = VIA1_BASE + 5
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000000r 2 VIA1_T1L_L = VIA1_BASE + 6
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000000r 2 VIA1_T1L_H = VIA1_BASE + 7
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000000r 2 VIA1_T2C_L = VIA1_BASE + 8
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000000r 2 VIA1_T2C_H = VIA1_BASE + 9
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000000r 2 VIA1_SR = VIA1_BASE + 10
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000000r 2 VIA1_ACR = VIA1_BASE + 11
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000000r 2 VIA1_PCR = VIA1_BASE + 12
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000000r 2 VIA1_IFR = VIA1_BASE + 13
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000000r 2 VIA1_IER = VIA1_BASE + 14
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000000r 2 VIA1_ORA_NH = VIA1_BASE + 15
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000000r 2 VIA1_IRA_NH = VIA1_BASE + 15
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000000r 2
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000000r 2 VIA2_BASE = $8120
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000000r 2 VIA2_ORB = VIA2_BASE
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000000r 2 VIA2_IRB = VIA2_BASE
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000000r 2 VIA2_ORA = VIA2_BASE + 1
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000000r 2 VIA2_IRA = VIA2_BASE + 1
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000000r 2 VIA2_DDRB = VIA2_BASE + 2
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000000r 2 VIA2_DDRA = VIA2_BASE + 3
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000000r 2 VIA2_T1C_L = VIA2_BASE + 4
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000000r 2 VIA2_T1C_H = VIA2_BASE + 5
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000000r 2 VIA2_T1L_L = VIA2_BASE + 6
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000000r 2 VIA2_T1L_H = VIA2_BASE + 7
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000000r 2 VIA2_T2C_L = VIA2_BASE + 8
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000000r 2 VIA2_T2C_H = VIA2_BASE + 9
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000000r 2 VIA2_SR = VIA2_BASE + 10
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000000r 2 VIA2_ACR = VIA2_BASE + 11
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000000r 2 VIA2_PCR = VIA2_BASE + 12
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000000r 2 VIA2_IFR = VIA2_BASE + 13
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000000r 2 VIA2_IER = VIA2_BASE + 14
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000000r 2 VIA2_ORA_NH = VIA2_BASE + 15
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000000r 2 VIA2_IRA_NH = VIA2_BASE + 15
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000000r 2
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000000r 2 ; Port bits
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000000r 2
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000000r 2 VIA_PA0 = (1 << 0)
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000000r 2 VIA_PA1 = (1 << 1)
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000000r 2 VIA_PA2 = (1 << 2)
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000000r 2 VIA_PA3 = (1 << 3)
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000000r 2 VIA_PA4 = (1 << 4)
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000000r 2 VIA_PA5 = (1 << 5)
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000000r 2 VIA_PA6 = (1 << 6)
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000000r 2 VIA_PA7 = (1 << 7)
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000000r 2
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000000r 2 ; Port bits
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000000r 2
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000000r 2 VIA_PB0 = 1 << 0
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000000r 2 VIA_PB1 = 1 << 1
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000000r 2 VIA_PB2 = 1 << 2
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000000r 2 VIA_PB3 = 1 << 3
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000000r 2 VIA_PB4 = 1 << 4
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000000r 2 VIA_PB5 = 1 << 5
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000000r 2 VIA_PB6 = 1 << 6
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000000r 2 VIA_PB7 = 1 << 7
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000000r 2
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000000r 1
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000000r 1 .segment "VECTORS"
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000000r 1
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000000r 1 rr rr .word nmi
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000002r 1 rr rr .word reset
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000004r 1 rr rr .word irq
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000006r 1
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000006r 1 .code
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000000r 1
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000000r 1 4C rr rr reset: jmp main
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000003r 1
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000003r 1 40 nmi: rti
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000004r 1
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000004r 1 40 irq: rti
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000005r 1
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000005r 1 main:
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000005r 1
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000005r 1 4C rr rr jmp lcd_init2
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000008r 1
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000008r 1
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000008r 1 loop:
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000008r 1
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000008r 1 4C rr rr jmp loop
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00000Br 1 lcd_init2:
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00000Br 1 A9 FF lda #$ff
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00000Dr 1 8D 21 81 sta VIA2_ORA
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000010r 1 8D 23 81 sta VIA2_DDRA
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000013r 1 A2 32 ldx #50
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000015r 1 20 rr rr jsr delay_ms
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000018r 1
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000018r 1 ;set register select bit to 0 for command/control
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000018r 1
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000018r 1 ;start init sequence
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000018r 1 A9 03 lda #$03
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00001Ar 1 20 rr rr jsr strobe_enable
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00001Dr 1 A2 05 ldx #5
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00001Fr 1 20 rr rr jsr delay_ms
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000022r 1
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000022r 1 A9 03 lda #$03
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000024r 1 20 rr rr jsr strobe_enable
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000027r 1 A2 05 ldx #5
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000029r 1 20 rr rr jsr delay_ms
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00002Cr 1
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00002Cr 1 A9 03 lda #$03
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00002Er 1 20 rr rr jsr strobe_enable
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000031r 1 A2 05 ldx #5
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000033r 1 20 rr rr jsr delay_ms
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000036r 1
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000036r 1 A9 02 lda #$02
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000038r 1 20 rr rr jsr strobe_enable
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00003Br 1 A2 03 ldx #3
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00003Dr 1 20 rr rr jsr delay_ms
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000040r 1
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000040r 1 ;now in 4 bit mode
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000040r 1
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000040r 1 ;function set
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000040r 1 A9 02 lda #$02 ;set data length to 4 bits
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000042r 1 20 rr rr jsr strobe_enable
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000045r 1
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000045r 1
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000045r 1 ;no delay needed here
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000045r 1
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000045r 1
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000045r 1 A9 08 lda #$08 ;2 lines 5x8 pixels
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000047r 1 20 rr rr jsr strobe_enable
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00004Ar 1 A2 03 ldx #3
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00004Cr 1 20 rr rr jsr delay_ms
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00004Fr 1
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00004Fr 1 A9 00 lda #$00 ;turn display off
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000051r 1 20 rr rr jsr strobe_enable
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000054r 1 A9 08 lda #$08
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000056r 1 20 rr rr jsr strobe_enable
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000059r 1 A2 03 ldx #3
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00005Br 1 20 rr rr jsr delay_ms
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00005Er 1
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00005Er 1 A9 00 lda #$00 ;clear display
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000060r 1 20 rr rr jsr strobe_enable
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000063r 1 A9 01 lda #$01
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000065r 1 20 rr rr jsr strobe_enable
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000068r 1 A2 03 ldx #3
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00006Ar 1 20 rr rr jsr delay_ms
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00006Dr 1
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00006Dr 1 A9 00 lda #$00 ;entry mode set
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00006Fr 1 20 rr rr jsr strobe_enable
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000072r 1 A9 06 lda #$06
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000074r 1 20 rr rr jsr strobe_enable
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000077r 1 A2 03 ldx #3
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000079r 1 20 rr rr jsr delay_ms
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00007Cr 1 ;end of initialization
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00007Cr 1
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00007Cr 1 A9 00 lda #$00 ;turn display on
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00007Er 1 20 rr rr jsr strobe_enable
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000081r 1 A9 0F lda #$0f ;display on, cursor on, blink on
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000083r 1 20 rr rr jsr strobe_enable
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000086r 1 A2 03 ldx #3
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000088r 1 20 rr rr jsr delay_ms
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00008Br 1
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00008Br 1 A9 00 lda #$00 ;CURSOR HOME
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00008Dr 1 20 rr rr jsr strobe_enable
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000090r 1 A9 02 lda #$02 ;cursor home
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000092r 1 20 rr rr jsr strobe_enable
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000095r 1 A2 03 ldx #3
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000097r 1 20 rr rr jsr delay_ms
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00009Ar 1
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00009Ar 1 4C rr rr jmp write_hello_world
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00009Dr 1
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00009Dr 1 write_hello_world:
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00009Dr 1 ;send H
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00009Dr 1 A9 14 lda #$14
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00009Fr 1 20 rr rr jsr strobe_enable
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0000A2r 1 A2 05 ldx #5
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0000A4r 1 20 rr rr jsr delay_ms
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0000A7r 1
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0000A7r 1 A9 18 lda #$18
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0000A9r 1 20 rr rr jsr strobe_enable
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0000ACr 1 A2 05 ldx #5
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0000AEr 1 20 rr rr jsr delay_ms
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0000B1r 1
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0000B1r 1 ;send E
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0000B1r 1 A9 14 lda #$14
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0000B3r 1 20 rr rr jsr strobe_enable
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0000B6r 1 A2 05 ldx #5
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0000B8r 1 20 rr rr jsr delay_ms
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0000BBr 1
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0000BBr 1 A9 15 lda #$15
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0000BDr 1 20 rr rr jsr strobe_enable
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0000C0r 1 A2 05 ldx #5
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0000C2r 1 20 rr rr jsr delay_ms
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0000C5r 1
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0000C5r 1 ;add in extra strobe for reading 8 status bits
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0000C5r 1 A9 00 lda #00
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0000C7r 1 20 rr rr jsr strobe_enable
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0000CAr 1 A9 00 lda #00
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0000CCr 1 20 rr rr jsr strobe_enable
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0000CFr 1
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0000CFr 1 ;send L
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0000CFr 1 A9 14 lda #$14
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0000D1r 1 20 rr rr jsr strobe_enable
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0000D4r 1 A2 05 ldx #5
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0000D6r 1 20 rr rr jsr delay_ms
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0000D9r 1
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0000D9r 1 A9 1C lda #$1C
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0000DBr 1 20 rr rr jsr strobe_enable
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0000DEr 1 A2 05 ldx #5
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0000E0r 1 20 rr rr jsr delay_ms
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0000E3r 1
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0000E3r 1 ;send L
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0000E3r 1 A9 14 lda #$14
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0000E5r 1 20 rr rr jsr strobe_enable
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0000E8r 1 A2 05 ldx #5
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0000EAr 1 20 rr rr jsr delay_ms
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0000EDr 1
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0000EDr 1 A9 1C lda #$1C
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0000EFr 1 20 rr rr jsr strobe_enable
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0000F2r 1 A2 05 ldx #5
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0000F4r 1 20 rr rr jsr delay_ms
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0000F7r 1
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0000F7r 1 ;send O
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0000F7r 1 A9 14 lda #$14
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0000F9r 1 20 rr rr jsr strobe_enable
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0000FCr 1 A2 05 ldx #5
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0000FEr 1 20 rr rr jsr delay_ms
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000101r 1
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000101r 1 A9 1F lda #$1F
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000103r 1 20 rr rr jsr strobe_enable
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000106r 1 A2 05 ldx #5
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000108r 1 20 rr rr jsr delay_ms
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00010Br 1
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00010Br 1 ;send space
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00010Br 1 A9 12 lda #$12
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00010Dr 1 20 rr rr jsr strobe_enable
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000110r 1 A2 05 ldx #5
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000112r 1 20 rr rr jsr delay_ms
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000115r 1
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000115r 1 A9 10 lda #$10
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000117r 1 20 rr rr jsr strobe_enable
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00011Ar 1 A2 05 ldx #5
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00011Cr 1 20 rr rr jsr delay_ms
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00011Fr 1
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00011Fr 1 ;send W
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00011Fr 1 A9 15 lda #$15
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000121r 1 20 rr rr jsr strobe_enable
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000124r 1 A2 05 ldx #5
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000126r 1 20 rr rr jsr delay_ms
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000129r 1
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000129r 1 A9 17 lda #$17
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00012Br 1 20 rr rr jsr strobe_enable
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00012Er 1 A2 05 ldx #5
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000130r 1 20 rr rr jsr delay_ms
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000133r 1
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000133r 1 ;send O
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000133r 1 A9 14 lda #$14
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000135r 1 20 rr rr jsr strobe_enable
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000138r 1 A2 05 ldx #5
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00013Ar 1 20 rr rr jsr delay_ms
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00013Dr 1
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00013Dr 1 A9 1F lda #$1F
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00013Fr 1 20 rr rr jsr strobe_enable
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000142r 1 A2 05 ldx #5
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000144r 1 20 rr rr jsr delay_ms
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000147r 1
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000147r 1 ;send R
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000147r 1 A9 15 lda #$15
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000149r 1 20 rr rr jsr strobe_enable
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00014Cr 1 A2 05 ldx #5
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00014Er 1 20 rr rr jsr delay_ms
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000151r 1
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000151r 1 A9 12 lda #$12
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000153r 1 20 rr rr jsr strobe_enable
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000156r 1 A2 05 ldx #5
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000158r 1 20 rr rr jsr delay_ms
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00015Br 1
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00015Br 1 ;send L
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00015Br 1 A9 14 lda #$14
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00015Dr 1 20 rr rr jsr strobe_enable
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000160r 1 A2 05 ldx #5
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000162r 1 20 rr rr jsr delay_ms
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000165r 1
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000165r 1 A9 1C lda #$1C
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000167r 1 20 rr rr jsr strobe_enable
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00016Ar 1 A2 05 ldx #5
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00016Cr 1 20 rr rr jsr delay_ms
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00016Fr 1
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00016Fr 1 ;send D
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00016Fr 1 A9 14 lda #$14
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000171r 1 20 rr rr jsr strobe_enable
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000174r 1 A2 05 ldx #5
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000176r 1 20 rr rr jsr delay_ms
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000179r 1
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000179r 1 A9 14 lda #$14
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00017Br 1 20 rr rr jsr strobe_enable
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00017Er 1 A2 05 ldx #5
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000180r 1 20 rr rr jsr delay_ms
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000183r 1
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000183r 1 ;send !
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000183r 1 A9 12 lda #$12
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000185r 1 20 rr rr jsr strobe_enable
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000188r 1 A2 05 ldx #5
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00018Ar 1 20 rr rr jsr delay_ms
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00018Dr 1
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00018Dr 1 A9 11 lda #$11
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00018Fr 1 20 rr rr jsr strobe_enable
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000192r 1 A2 05 ldx #5
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000194r 1 20 rr rr jsr delay_ms
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000197r 1
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000197r 1 4C rr rr jmp loop
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00019Ar 1
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00019Ar 1 strobe_enable:
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00019Ar 1 09 20 ora #$20 ;add enable bit
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00019Cr 1 8D 21 81 sta VIA2_ORA ;send value out to via
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00019Fr 1 A2 0A ldx #10
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0001A1r 1 20 rr rr jsr delay_ms
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0001A4r 1 29 DF and #$DF ;mask to take out enable
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0001A6r 1 8D 21 81 sta VIA2_ORA ;take out enable bit and send to via
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0001A9r 1
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0001A9r 1 60 rts
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0001AAr 1
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0001AAr 1 ; Delay the number of miliseconds specified by X
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0001AAr 1 ; This is hardcoded for a 1 MHz system clock
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0001AAr 1 48 delay_ms: pha ; 3
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0001ABr 1 8A txa ; 2
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0001ACr 1 48 pha ; 3
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0001ADr 1 98 tya ; 2
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0001AEr 1 48 pha ; 3
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0001AFr 1
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0001AFr 1 A4 00 ldy $00 ; 3 (dummy operation)
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0001B1r 1 A0 BE ldy #190 ; 2
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0001B3r 1 88 @loop1: dey ; 190 * 2
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0001B4r 1 D0 FD bne @loop1 ; 190 * 3 - 1
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0001B6r 1
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0001B6r 1 CA @loop2: dex ; 2
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0001B7r 1 F0 09 beq @return ; (x - 1) * 2 + 3
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0001B9r 1
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0001B9r 1 EA nop ; 2
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0001BAr 1 A0 C6 ldy #198 ; 2
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0001BCr 1 88 @loop3: dey ; 198 * 2
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0001BDr 1 D0 FD bne @loop3 ; 198 * 3 - 1
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0001BFr 1
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0001BFr 1 4C rr rr jmp @loop2 ; 3
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0001C2r 1
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0001C2r 1 68 @return: pla ; 4
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0001C3r 1 A8 tay ; 2
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0001C4r 1 68 pla ; 4
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0001C5r 1 AA tax ; 2
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0001C6r 1 68 pla ; 4
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0001C7r 1 60 rts ; 6 (+ 6 for JSR)
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0001C7r 1
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