verilog-apple-one/rtl/uart/uart.v

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//
// Just add the .v file to the project
//
//
//`include "./async_tx_rx.v"
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module uart(
input clk,
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input reset,
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input enable,
input [1:0] address,
input w_en,
input [7:0] din,
output reg [7:0] dout,
input uart_rx,
output uart_tx,
output uart_cts
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);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 8;
reg uart_tx_stb;
reg [7:0] uart_tx_byte;
wire uart_tx_status;
async_transmitter #(ClkFrequency, Baud) my_tx (
.clk(clk),
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.reset(reset),
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.TxD_start(uart_tx_stb),
.TxD_data(uart_tx_byte),
.TxD(uart_tx),
.TxD_busy(uart_tx_status)
);
wire uart_rx_stb, rx_idle, rx_end;
wire [7:0] rx_data;
reg uart_rx_status, uart_rx_ack;
reg [7:0] uart_rx_byte;
async_receiver #(ClkFrequency, Baud, Oversampling) my_rx(
.clk(clk),
.RxD(uart_rx),
.RxD_data_ready(uart_rx_stb),
.RxD_data(rx_data),
.RxD_idle(rx_idle),
.RxD_endofpacket(rx_end)
);
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always @(posedge clk or posedge reset)
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begin
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if (reset)
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begin
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uart_rx_status <= 'b0;
uart_rx_byte <= 8'd0;
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end
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else
begin
// new byte from RX, check register is clear and CPU has seen
// previous byte, otherwise we ignore the new data
if (uart_rx_stb && ~uart_rx_status)
begin
uart_rx_status <= 'b1;
uart_rx_byte <= rx_data;
end
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// clear the rx status flag on ack from CPU
if (uart_rx_ack)
uart_rx_status <= 'b0;
end
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end
assign uart_cts = ~rx_idle || uart_rx_status;
localparam UART_RX = 2'b00;
localparam UART_RXCR = 2'b01;
localparam UART_TX = 2'b10;
// Handle Register
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always @(posedge clk or posedge reset)
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begin
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if (reset)
begin
dout <= 8'd0;
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uart_tx_stb <= 0;
uart_rx_ack <= 0;
uart_tx_byte <= 8'd0;
end
else
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begin
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uart_tx_stb <= 0;
uart_rx_ack <= 0;
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if (enable)
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begin
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case (address)
UART_TX:
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begin
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// UART TX - 0xD012
dout <= {uart_tx_status, 7'd0};
if (w_en)
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begin
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// Apple 1 terminal only uses 7 bits, MSB indicates
// terminal has ack'd RX
if (~uart_tx_status)
begin
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end
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end
end
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UART_RXCR:
begin
// UART RX CR - 0xD011
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dout <= {uart_rx_status, 7'b0};
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end
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UART_RX:
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begin
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// UART RX - 0xD010
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dout <= {uart_rx_status, uart_rx_byte[6:0]};
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if (~w_en)
uart_rx_ack <= 1'b1;
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end
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default:
dout <= 8'b0;
endcase
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end
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else
dout <= 8'b0;
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end
end
endmodule