mirror of
https://github.com/alangarf/apple-one.git
synced 2024-06-06 16:29:33 +00:00
Cleaned up mess, and added HX8K board top file
This commit is contained in:
Alan Garfield
parent
305d9b614b
commit
149334259d
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@ -4,7 +4,7 @@ Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Bui
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ProjectName=appleone
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Vendor=SiliconBlue
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Synthesis=synplify
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ProjectVFiles=../../../rtl/apple1_top.v=work,../../../rtl/boards/ice40hx8k/clocks.v=work,../../../rtl/boards/ice40hx8k/clock_pll.v=work,../../../rtl/cpu/ALU.v=work,../../../rtl/cpu/cpu.v=work,../../../rtl/rom_wozmon.v,../../../rtl/uart/uart.v,../../../rtl/ram.v
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ProjectVFiles=../../rtl/rom_wozmon.v,../../rtl/apple1.v,../../rtl/ram.v,../../rtl/boards/ice40hx8k/apple1_top.v,../../rtl/boards/ice40hx8k/clock_pll.v,../../rtl/cpu/ALU.v,../../rtl/cpu/cpu.v,../../rtl/uart/async_tx_rx.v,../../rtl/uart/uart.v
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ProjectCFiles=appleone_syn.sdc
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CurImplementation=appleone_Implmnt
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Implementations=appleone_Implmnt
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@ -19,13 +19,13 @@ DevicePower=
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NetlistFile=appleone_Implmnt/appleone.edf
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AdditionalEDIFFile=
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IPEDIFFile=
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DesignLib=appleone_Implmnt/sbt/netlist/oadb-top
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DesignView=_rt
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DesignCell=top
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DesignLib=
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DesignView=
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DesignCell=
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SynthesisSDCFile=appleone_Implmnt/appleone.scf
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UserPinConstraintFile=
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UserSDCFile=
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PhysicalConstraintFile=../../../ice40hx8k.pcf
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PhysicalConstraintFile=
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BackendImplPathName=
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Devicevoltage=1.14
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DevicevoltagePerformance=+/-5%(datasheet default)
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@ -84,5 +84,5 @@ BitmapSetSecurity=no
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BitmapSetNoUsedIONoPullup=no
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FloorPlannerShowFanInNets=yes
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FloorPlannerShowFanOutNets=yes
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HookTo3rdPartyTextEditor=
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HookTo3rdPartyTextEditor=no
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@ -1,15 +1,16 @@
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#-- Synopsys, Inc.
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#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone\appleone_syn.prj
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#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone_syn.prj
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#project files
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add_file -verilog -lib work "../../../rtl/apple1_top.v"
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add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clocks.v"
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add_file -verilog -lib work "../../../rtl/boards/ice40hx8k/clock_pll.v"
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add_file -verilog -lib work "../../../rtl/cpu/ALU.v"
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add_file -verilog -lib work "../../../rtl/cpu/cpu.v"
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add_file -verilog -lib work "../../../rtl/rom_wozmon.v"
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add_file -verilog -lib work "../../../rtl/uart/uart.v"
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add_file -verilog -lib work "../../../rtl/ram.v"
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add_file -verilog -lib work "../../rtl/rom_wozmon.v"
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add_file -verilog -lib work "../../rtl/apple1.v"
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add_file -verilog -lib work "../../rtl/ram.v"
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add_file -verilog -lib work "../../rtl/boards/ice40hx8k/apple1_top.v"
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add_file -verilog -lib work "../../rtl/boards/ice40hx8k/clock_pll.v"
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add_file -verilog -lib work "../../rtl/cpu/ALU.v"
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add_file -verilog -lib work "../../rtl/cpu/cpu.v"
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add_file -verilog -lib work "../../rtl/uart/async_tx_rx.v"
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add_file -verilog -lib work "../../rtl/uart/uart.v"
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add_file -constraint -lib work "appleone_syn.sdc"
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#implementation: "appleone_Implmnt"
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impl -add appleone_Implmnt -type fpga
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@ -1,22 +1,10 @@
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//
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// FIXME:
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// there defines must be enabled in the project
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// settings to avoid conflicts with different
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// development platforms
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//
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//`define ICE40
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//
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module top(
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module apple1(
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input clk25, // 25 MHz master clock
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input rst_n, // active low synchronous reset (needed for simulation)
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input uart_rx,
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output uart_tx,
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output uart_cts,
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output [7:0] led, // what do these do?
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output [7:0] ledx // what do these do?
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output uart_cts
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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@ -28,23 +16,6 @@ module top(
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//////////////////////////////////////////////////////////////////////////
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// Clocks
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reg cpu_clken;
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// FIXME:
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// the clocks here should come from higher up
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// the hierarchy, i.e. generated at the board
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// level.
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//
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// if cpu_clken is a simple block,
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// keep it here but make it generic.
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`ifdef ICE40
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clocks my_clocks(
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.clk(clk),
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.clk25(clk25),
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.cpu_clken(cpu_clken)
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);
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`endif
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// generate clock enable once every
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// 25 clocks. This will (hopefully) make
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@ -56,6 +27,7 @@ module top(
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//
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reg [4:0] clk_div;
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reg cpu_clken;
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always @(posedge clk25)
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begin
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// note: clk_div should be compared to
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@ -107,8 +79,8 @@ module top(
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.DI (dbi_c),
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.DO (dbo_c),
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.WE (we_c),
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.IRQ (1'b0),
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.NMI (1'b0),
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.IRQ (1'b1),
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.NMI (1'b1),
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.RDY (cpu_clken)
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);
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@ -162,8 +134,7 @@ module top(
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.address(ab[1:0]),
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.w_en(we & uart_cs),
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.din(dbo),
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.dout(uart_dout),
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.led(led)
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.dout(uart_dout)
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);
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// link up chip selected device to cpu input
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@ -171,60 +142,4 @@ module top(
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rom_cs ? rom_dout :
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uart_cs ? uart_dout :
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8'hFF;
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assign ledx = ab[7:0];
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// always @(posedge clk25)
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// begin
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// if (cpu_clken)
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// begin
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// led <= ab[7:0];
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// ledx <= ~ab[15:8];
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// end
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// end
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// reg [7:0] ram[0:8191] /* synthesis syn_ramstyle = "block_ram" */;
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// reg [7:0] rom[0:255] /* synthesis syn_ramstyle = "block_ram" */;
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// reg [7:0] basic[0:4095] /* synthesis syn_ramstyle = "block_ram" */;
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//
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// initial begin
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// $readmemh("../roms/ram.hex", ram, 0, 8191);
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// $readmemh("../roms/rom.hex", rom, 0, 255);
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// $readmemh("../roms/basic.hex", basic, 0, 4095);
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// end
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//
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// always @(posedge clk_25)
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// begin
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// if (phi_clk_en)
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// begin
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// if (res)
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// begin
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// case(ab)
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// default:
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// begin
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// if (ab[15:12] == 4'b0000 || ab[15:12] == 4'b0001)
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// begin
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// // 0x0000 -> 0x1FFF - RAM
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// dbi <= ram[ab[12:0]];
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// if (~rw) ram[ab[12:0]] <= dbo;
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// end
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// else if (ab[15:12] == 4'b1110)
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// begin
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// // 0xE000 -> 0xEFFF - BASIC
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// dbi <= basic[ab[11:0]];
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// end
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// else if (ab[15:8] == 8'b11111111)
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// begin
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// // 0xFF00 -> 0xFFFF - ROM
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// dbi <= rom[ab[7:0]];
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// end
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// else
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// // unknown address return zero
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// dbi <= 8'h0;
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// end
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//
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// endcase
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// end
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// end
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// end
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endmodule
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28
rtl/boards/ice40hx8k/apple1_top.v
Normal file
28
rtl/boards/ice40hx8k/apple1_top.v
Normal file
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@ -0,0 +1,28 @@
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module apple1_top(
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input clk, // 12 MHz board clock
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input uart_rx,
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output uart_tx,
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output uart_cts
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);
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wire clk25;
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// 12MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTCORE(),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts)
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);
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endmodule
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@ -1,34 +0,0 @@
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module clocks (
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input clk,
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output clk25,
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output reg cpu_clken
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);
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// 12MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTCORE(),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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reg [25:0] clk_div;
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always @(posedge clk25)
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begin
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if (clk_div == 12000000)
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clk_div <= 0;
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else
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clk_div <= clk_div + 1;
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// 1MHz
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cpu_clken <= (clk_div[25:0] == 0);
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// 2MHz
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//cpu_clken <= (clk_div[4] == 0) & (clk_div[2:0] == 0);
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// 4MHz
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//cpu_clken <= (clk_div[4] == 0) & (clk_div[1:0] == 0);
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end
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endmodule
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@ -15,8 +15,7 @@ module uart(
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input uart_rx,
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output uart_tx,
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output uart_cts,
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output reg [7:0] led
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output uart_cts
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);
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parameter ClkFrequency = 25000000; // 25MHz
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@ -76,8 +75,6 @@ module uart(
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uart_tx_stb <= 0;
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uart_rx_ack <= 0;
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led[7] <= uart_rx_status;
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if (enable)
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begin
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case (address)
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@ -113,7 +110,6 @@ module uart(
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begin
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dout <= {uart_rx_status, uart_rx_byte[6:0]};
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uart_rx_ack <= 1'b1;
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led[6:0] <= uart_rx_byte[6:0];
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end
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end
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endcase
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