Apple-1-HW/verilog-apple-one
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Updated DE0 top level and Quartus DE0 project to new directory layout

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This commit is contained in:
Niels Moseley 2018-01-27 16:01:27 +01:00
parent a60620e6ec
commit 0527dbb999
2 changed files with 5 additions and 2 deletions
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5
boards/terasic_de0/apple-one.qsf
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@ -344,6 +344,10 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/cpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/ALU.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet_6502.v
set_global_assignment -name VERILOG_FILE ../../rtl/apple1.v
set_global_assignment -name SDC_FILE "apple-one.sdc"
set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/apple1_de0_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/cpu.v
@ -352,5 +356,4 @@ set_global_assignment -name VERILOG_FILE ../../rtl/uart/uart.v
set_global_assignment -name VERILOG_FILE ../../rtl/uart/async_tx_rx.v
set_global_assignment -name VERILOG_FILE ../../rtl/rom_wozmon.v
set_global_assignment -name VERILOG_FILE ../../rtl/ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/apple1_top.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
rtl/boards/terasic_de0/apple1_de0_top.v
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@ -43,7 +43,7 @@ module apple1_de0_top(
//////////////////////////////////////////////////////////////////////////
// Core of system
top core_top(
apple1 apple1_top(
.clk25(clk25),
.rst_n(1'b1), // we don't have any reset pulse..
.uart_rx(UART_RXD),