Apple-1-HW/verilog-apple-one
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fixed param paths for yosys, may need more work

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This commit is contained in:
Alan Garfield 2018-02-14 15:27:36 +11:00
parent 78b3c6f5c6
commit 526538a685
13 changed files with 74 additions and 116 deletions
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32
boards/ice40hx8k-b-evn/ice40hx8k.pcf
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@ -19,22 +19,6 @@ set_io led[2] C4
set_io led[1] B3 set_io led[1] B3
set_io led[0] C3 set_io led[0] C3
### YL-4 Switch Matrix LEDs (inverted)
set_io ledx[7] J1
set_io ledx[6] J2
set_io ledx[5] K1
set_io ledx[4] K3
set_io ledx[3] L1
set_io ledx[2] L3
set_io ledx[1] M1
set_io ledx[0] M2
### YL-4 Switch Marix Buttons
set_io button[3] E2
set_io button[2] F1
set_io button[1] F2
set_io button[0] G1
### PS2 Keyboard ### PS2 Keyboard
set_io ps2_clk N3 set_io ps2_clk N3
set_io ps2_din N2 set_io ps2_din N2
@ -46,6 +30,22 @@ set_io vga_red B1
set_io vga_grn B2 set_io vga_grn B2
set_io vga_blu C1 set_io vga_blu C1
### YL-4 Switch Marix Buttons
set_io button[3] E2
set_io button[2] F1
set_io button[1] F2
set_io button[0] G1
### YL-4 Switch Matrix LEDs (inverted)
set_io ledx[7] J1
set_io ledx[6] J2
set_io ledx[5] K1
set_io ledx[4] K3
set_io ledx[3] L1
set_io ledx[2] L3
set_io ledx[1] M1
set_io ledx[0] M2
### TM1638 Display ### TM1638 Display
#set_io tm_clk P1 #set_io tm_clk P1
#set_io tm_dio P2 #set_io tm_dio P2

23
boards/ice40hx8k-b-evn/yosys/Makefile
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@ -1,9 +1,15 @@
DEVICE = hx8k DEVICE = 8k
PIN_DEF=ice40hx8k.pcf PACKAGE = ct256
FREQ_OSC = 12
FREQ_PLL = 25
PIN_DEF = ice40hx8k.pcf
SOURCEDIR = ../../../rtl SOURCEDIR = ../../../rtl
BUILDDIR = build BUILDDIR = build
PLL = $(BUILDDIR)/pll.sv
all: apple1 prog all: apple1 prog
info: info:
@ -17,10 +23,10 @@ dir:
# ------ TEMPLATES ------ # ------ TEMPLATES ------
$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v $(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^ yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^
$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif $(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^ arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc $(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
icepack $^ $@ icepack $^ $@
@ -34,8 +40,11 @@ $(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
%_tb.vcd: %_tb.vvp %_tb.vcd: %_tb.vvp
vvp -N $< +vcd=$@ vvp -N $< +vcd=$@
$(PLL):
icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
# ------ APPLE 1 ------ # ------ APPLE 1 ------
apple1: dir $(BUILDDIR)/apple1.bin apple1: dir $(PLL) $(BUILDDIR)/apple1.bin
report: dir apple1.rpt report: dir apple1.rpt
$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc $(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
@ -56,8 +65,8 @@ $(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
$(SOURCEDIR)/vga/font_rom.v \ $(SOURCEDIR)/vga/font_rom.v \
$(SOURCEDIR)/ps2keyboard/debounce.v \ $(SOURCEDIR)/ps2keyboard/debounce.v \
$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \ $(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
$(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \ $(SOURCEDIR)/boards/ice40hx8k-b-evn/apple1_hx8k.v \
$(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v $(BUILDDIR)/pll.sv
apple1.rpt: $(BUILDDIR)/apple1.asc apple1.rpt: $(BUILDDIR)/apple1.asc

16
rtl/apple1.v
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@ -23,11 +23,11 @@
// //
module apple1 #( module apple1 #(
parameter BASIC_FILENAME = "", parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "", parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "", parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "", parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "" parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) ( ) (
input clk25, // 25 MHz master clock input clk25, // 25 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation) input rst_n, // active low synchronous reset (needed for simulation)
@ -138,7 +138,7 @@ module apple1 #(
// WozMon ROM // WozMon ROM
wire [7:0] rom_dout; wire [7:0] rom_dout;
rom_wozmon #( rom_wozmon #(
.ROM_FILENAME (WOZMON_ROM_FILENAME) .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
) my_rom_wozmon( ) my_rom_wozmon(
.clk(clk25), .clk(clk25),
.address(ab[7:0]), .address(ab[7:0]),
@ -198,8 +198,8 @@ module apple1 #(
// VGA Display interface // VGA Display interface
reg [1:0] vga_mode; reg [1:0] vga_mode;
vga #( vga #(
.RAM_FILENAME (VRAM_FILENAME), .VRAM_FILENAME (VRAM_FILENAME),
.ROM_FILENAME (FONT_ROM_FILENAME) .FONT_ROM_FILENAME (FONT_ROM_FILENAME)
) my_vga( ) my_vga(
.clk25(clk25), .clk25(clk25),
.enable(vga_cs & cpu_clken), .enable(vga_cs & cpu_clken),

11
rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v
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@ -56,11 +56,10 @@ module apple1_top #(
wire clk25; wire clk25;
// 12MHz up to 25MHz // 12MHz up to 25MHz
clock_pll clock_pll_inst( pll my_pll(
.REFERENCECLK(clk), .clock_in(clk),
.PLLOUTGLOBAL(clk25), .clock_out(clk25)
.RESET(1'b1) );
);
wire [15:0] pc_monitor; wire [15:0] pc_monitor;
assign led[7:0] = pc_monitor[7:0]; assign led[7:0] = pc_monitor[7:0];
@ -99,7 +98,7 @@ module apple1_top #(
.uart_cts(uart_cts), .uart_cts(uart_cts),
.ps2_clk(ps2__clk), .ps2_clk(ps2__clk),
.ps2_din(ps2__din), .ps2_din(ps2__din),
.ps2_select(1'b0), .ps2_select(1'b1),
.vga_h_sync(vga_h_sync), .vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync), .vga_v_sync(vga_v_sync),
.vga_red(vga_red), .vga_red(vga_red),

38
rtl/boards/ice40hx8k-b-evn/clock_pll.v
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@ -1,38 +0,0 @@
module clock_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=12, Fout=25;
defparam clock_pll_inst.DIVR = 4'b0000;
defparam clock_pll_inst.DIVF = 7'b1000010;
defparam clock_pll_inst.DIVQ = 3'b101;
defparam clock_pll_inst.FILTER_RANGE = 3'b001;
defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule

4
rtl/boards/ice40hx8k-b-evn/clock_pll_inst.v
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@ -1,4 +0,0 @@
clock_pll clock_pll_inst(.REFERENCECLK(),
.PLLOUTCORE(),
.PLLOUTGLOBAL(),
.RESET());

5
rtl/boards/ice40hx8k-b-evn/clock_pll_v.lpc
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@ -1,5 +0,0 @@
[General]
DeviceFamily=iCE40
[AdditionalDelay]
AdditionalDelayNo=true

8
rtl/ram.v
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@ -22,15 +22,15 @@
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
module ram( module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk, // clock signal input clk, // clock signal
input [12:0] address, // address bus input [12:0] address, // address bus
input w_en, // active high write enable strobe input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input) input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout // 8-bit data bus (output) output reg [7:0] dout // 8-bit data bus (output)
); );
parameter RAM_FILENAME = "";
reg [7:0] ram_data[0:8191]; reg [7:0] ram_data[0:8191];

8
rtl/rom_basic.v
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@ -22,13 +22,13 @@
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
module rom_basic( module rom_basic #(
parameter BASIC_FILENAME = "../../../roms/basic.hex"
) (
input clk, // clock signal input clk, // clock signal
input [11:0] address, // address bus input [11:0] address, // address bus
output reg [7:0] dout // 8-bit data bus (output) output reg [7:0] dout // 8-bit data bus (output)
); );
parameter BASIC_FILENAME = "";
reg [7:0] rom_data[0:4095]; reg [7:0] rom_data[0:4095];

10
rtl/rom_wozmon.v
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@ -22,18 +22,18 @@
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
module rom_wozmon( module rom_wozmon #(
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input clk, // clock signal input clk, // clock signal
input [7:0] address, // address bus input [7:0] address, // address bus
output reg [7:0] dout // 8-bit data bus (output) output reg [7:0] dout // 8-bit data bus (output)
); );
parameter ROM_FILENAME = "";
reg [7:0] rom_data[0:255]; reg [7:0] rom_data[0:255];
initial initial
$readmemh(ROM_FILENAME, rom_data, 0, 255); $readmemh(WOZMON_ROM_FILENAME, rom_data, 0, 255);
always @(posedge clk) always @(posedge clk)
dout <= rom_data[address]; dout <= rom_data[address];

11
rtl/vga/font_rom.v
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@ -20,11 +20,10 @@
// Author.....: Alan Garfield // Author.....: Alan Garfield
// Date.......: 3-2-2018 // Date.......: 3-2-2018
// //
//`define DOTTY
//`define SCANLINES
`define NORMAL
module font_rom( module font_rom #(
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
) (
input clk, // clock signal input clk, // clock signal
input [1:0] mode, // character mode input [1:0] mode, // character mode
input [5:0] character, // address bus input [5:0] character, // address bus
@ -33,12 +32,10 @@ module font_rom(
output reg out // single pixel from address and pixel pos output reg out // single pixel from address and pixel pos
); );
parameter ROM_FILENAME = "";
reg [7:0] rom[0:1023]; reg [7:0] rom[0:1023];
initial initial
$readmemh(ROM_FILENAME, rom, 0, 1023); $readmemh(FONT_ROM_FILENAME, rom, 0, 1023);
// double height of pixel by ignoring bit 0 // double height of pixel by ignoring bit 0
wire [3:0] line_ptr = line[4:1]; wire [3:0] line_ptr = line[4:1];

14
rtl/vga/vga.v
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@ -1,4 +1,7 @@
module vga( module vga #(
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex"
) (
input clk25, // clock signal input clk25, // clock signal
input enable, // clock enable strobe, input enable, // clock enable strobe,
input rst, // active high reset signal input rst, // active high reset signal
@ -11,7 +14,7 @@ module vga(
input w_en, // active high write enable strobe input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input) input [7:0] din, // 8-bit data bus (input)
input [1:0] mode // 2-bit mode setting for pixel doubling input [1:0] mode // 2-bit mode setting for pixel doubling
); );
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Registers and Parameters // Registers and Parameters
@ -26,9 +29,6 @@ module vga(
parameter vbp = 31; // end of vertical back porch parameter vbp = 31; // end of vertical back porch
parameter vfp = 511; // beginning of vertical front porch parameter vfp = 511; // beginning of vertical front porch
// Video RAM contents
parameter RAM_FILENAME = "";
// registers for storing the horizontal & vertical counters // registers for storing the horizontal & vertical counters
reg [9:0] h_cnt; reg [9:0] h_cnt;
reg [9:0] v_cnt; reg [9:0] v_cnt;
@ -123,7 +123,7 @@ module vga(
// Character ROM // Character ROM
font_rom #( font_rom #(
.ROM_FILENAME (ROM_FILENAME) .FONT_ROM_FILENAME (FONT_ROM_FILENAME)
) my_font_rom( ) my_font_rom(
.clk(clk25), .clk(clk25),
.mode(mode), .mode(mode),
@ -137,7 +137,7 @@ module vga(
// Video RAM // Video RAM
vram #( vram #(
.RAM_FILENAME (RAM_FILENAME) .VRAM_FILENAME (VRAM_FILENAME)
) my_vram( ) my_vram(
.clk(clk25), .clk(clk25),
.read_addr(vram_r_addr), .read_addr(vram_r_addr),

10
rtl/vga/vram.v
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@ -22,7 +22,9 @@
// Date.......: 26-1-2018 // Date.......: 26-1-2018
// //
module vram( module vram #(
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
) (
input clk, // clock signal input clk, // clock signal
input [10:0] read_addr, // read address bus input [10:0] read_addr, // read address bus
input [10:0] write_addr, // write address bus input [10:0] write_addr, // write address bus
@ -30,14 +32,12 @@ module vram(
input w_en, // active high write enable strobe input w_en, // active high write enable strobe
input [5:0] din, // 6-bit data bus (input) input [5:0] din, // 6-bit data bus (input)
output reg [5:0] dout // 6-bit data bus (output) output reg [5:0] dout // 6-bit data bus (output)
); );
parameter RAM_FILENAME = "";
reg [5:0] ram_data[0:2047]; reg [5:0] ram_data[0:2047];
initial initial
$readmemb(RAM_FILENAME, ram_data, 0, 2047); $readmemb(VRAM_FILENAME, ram_data, 0, 2047);
always @(posedge clk) always @(posedge clk)
begin begin