Apple-1-HW/verilog-apple-one
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Added missing 7-segment display driver for DE0 board

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This commit is contained in:
Niels Moseley 2018-01-27 18:47:56 +01:00
parent c244a3bc5d
commit 645ec26081
2 changed files with 77 additions and 1 deletions
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2
rtl/apple1.v
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@ -39,7 +39,7 @@ module apple1(
begin
// note: clk_div should be compared to
// N-1, where N is the clock divisor
if ((clk_div == 4999999) || (rst_n == 1'b0))
if ((clk_div == 24999999) || (rst_n == 1'b0))
clk_div <= 0;
else
clk_div <= clk_div + 1'b1;

76
rtl/boards/terasic_de0/segmentdisplay.v Normal file
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@ -0,0 +1,76 @@
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//
// Description: 7-segment display driver for DE0 board
//
// Author.....: Niels A. Moseley
// Date.......: 26-1-2018
//
module segmentdisplay (
clk,
latch,
hexdigit_in,
display_out
);
input clk,latch;
input [3:0] hexdigit_in;
output reg [0:6] display_out;
always @(posedge clk)
begin
if (latch == 1)
begin
case (hexdigit_in)
4'b0000:
display_out <= 7'b1000000;
4'b0001:
display_out <= 7'b1111001;
4'b0010:
display_out <= 7'b0100100;
4'b0011:
display_out <= 7'b0110000;
4'b0100:
display_out <= 7'b0011001;
4'b0101:
display_out <= 7'b0010010;
4'b0110:
display_out <= 7'b0000010;
4'b0111:
display_out <= 7'b1111000;
4'b1000:
display_out <= 7'b0000000;
4'b1001:
display_out <= 7'b0011000;
4'b1010:
display_out <= 7'b0001000;
4'b1011:
display_out <= 7'b0000011;
4'b1100:
display_out <= 7'b1000110;
4'b1101:
display_out <= 7'b0100001;
4'b1110:
display_out <= 7'b0000110;
4'b1111:
display_out <= 7'b0001110;
endcase
end
end
endmodule