mirror of
https://github.com/alangarf/apple-one.git
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Support for TinyFPGA B2 with computer board
This commit is contained in:
Miodrag Milanovic
parent
7d36183103
commit
657fbc69b4
72
boards/tinyfpga_yosys/Makefile
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72
boards/tinyfpga_yosys/Makefile
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DEVICE = lp8k
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PIN_DEF=tinyfpga.pcf
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SOURCEDIR = ../../rtl
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BUILDDIR = build
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all: apple1 prog
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info:
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@echo " To build: make apple1"
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@echo " To program: make prog"
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@echo "To build report: make report"
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@echo " To clean up: make clean"
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dir:
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mkdir -p $(BUILDDIR)
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
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yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
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$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
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arachne-pnr -d 8k -P cm81 -o $@ -p $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -mtr $@ $<
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%_tb.vvp: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
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$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/clock.v \
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$(SOURCEDIR)/pwr_reset.v \
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$(SOURCEDIR)/ram.v \
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$(SOURCEDIR)/rom_wozmon.v \
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$(SOURCEDIR)/rom_basic.v \
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$(SOURCEDIR)/cpu/arlet_6502.v \
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$(SOURCEDIR)/cpu/arlet/ALU.v \
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$(SOURCEDIR)/cpu/arlet/cpu.v \
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$(SOURCEDIR)/uart/uart.v \
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$(SOURCEDIR)/uart/async_tx_rx.v \
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$(SOURCEDIR)/vga/vga.v \
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$(SOURCEDIR)/vga/vram.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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clock_pll.v \
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apple1_hx8k.v
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apple1.rpt: $(BUILDDIR)/apple1.asc
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prog: dir $(BUILDDIR)/apple1.bin
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tinyfpgab -p $(filter-out $<,$^)
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# ------ HELPERS ------
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clean:
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rm -rf build apple1.rpt
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.SECONDARY:
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.PHONY: all info clean prog iceprog
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92
boards/tinyfpga_yosys/apple1_hx8k.v
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92
boards/tinyfpga_yosys/apple1_hx8k.v
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Miodrag Milanovic
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// Date.......: 11-2-2018
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//
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module apple1_top(
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input pin3_clk_16mhz,// 16 MHz board clock
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// Outputs to VGA display
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output pin4, // hozizontal VGA sync pulse
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output pin5, // vertical VGA sync pulse
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input pin6, // PS/2 data input
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input pin7, // PS/2 clock
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// I/O interface to computer
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input pin11, // asynchronous serial data input from computer
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output pin12, // asynchronous serial data output to computer
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output pin13, // clear to send flag to computer
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output reg pin24, // red VGA signal
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output reg pin23, // red VGA signal
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output reg pin22, // green VGA signal
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output reg pin21, // green VGA signal
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output reg pin20, // blue VGA signal
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output reg pin19 // blue VGA signal
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);
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wire clk25;
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// 16MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(pin3_clk_16mhz),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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wire [15:0] pc_monitor;
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reg [1:0] button = 2'b01;
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wire vga_red;
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wire vga_grn;
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wire vga_blu;
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(button[0]),
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.ps2_clk(pin7),
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.ps2_din(pin6),
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.ps2_select(1'b0),
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.uart_rx(pin11),
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.uart_tx(pin12),
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.uart_cts(pin13),
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.clr_screen_btn(button[1]),
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.vga_h_sync(pin4),
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.vga_v_sync(pin5),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu),
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.pc_monitor(pc_monitor)
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);
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assign pin19 = vga_blu;
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assign pin20 = vga_blu;
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assign pin21 = vga_grn;
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assign pin22 = vga_grn;
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assign pin23 = vga_red;
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assign pin24 = vga_red;
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endmodule
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38
boards/tinyfpga_yosys/clock_pll.v
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38
boards/tinyfpga_yosys/clock_pll.v
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module clock_pll(REFERENCECLK,
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PLLOUTCORE,
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PLLOUTGLOBAL,
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RESET);
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input REFERENCECLK;
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input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
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output PLLOUTCORE;
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output PLLOUTGLOBAL;
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SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
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.PLLOUTCORE(PLLOUTCORE),
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.PLLOUTGLOBAL(PLLOUTGLOBAL),
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.EXTFEEDBACK(),
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.DYNAMICDELAY(),
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.RESETB(RESET),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(),
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.LOCK(),
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.SDI(),
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.SDO(),
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.SCLK());
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//\\ Fin=16, Fout=25;
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defparam clock_pll_inst.DIVR = 4'b0000;
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defparam clock_pll_inst.DIVF = 7'b0110001;
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defparam clock_pll_inst.DIVQ = 3'b101;
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defparam clock_pll_inst.FILTER_RANGE = 3'b001;
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defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
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defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
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defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
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endmodule
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29
boards/tinyfpga_yosys/tinyfpga.pcf
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29
boards/tinyfpga_yosys/tinyfpga.pcf
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# For the TinyFPGA Computer Project Board
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### left side of board
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#set_io --warn-no-port pin1_usb_dp A3
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#set_io --warn-no-port pin2_usb_dn A4
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set_io --warn-no-port pin3_clk_16mhz B4
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set_io --warn-no-port pin4 B2
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set_io --warn-no-port pin5 A2
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set_io --warn-no-port pin6 A1
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set_io --warn-no-port pin7 B1
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#set_io --warn-no-port pin8 C1
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#set_io --warn-no-port pin9 D1
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#set_io --warn-no-port pin10 E1
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set_io --warn-no-port pin11 G1
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set_io --warn-no-port pin12 H1
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set_io --warn-no-port pin13 J1
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### right side of board
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#set_io --warn-no-port pin14_sdo G6
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#set_io --warn-no-port pin15_sdi H7
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#set_io --warn-no-port pin16_sck G7
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#set_io --warn-no-port pin17_ss F7
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#set_io --warn-no-port pin18 D9
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set_io --warn-no-port pin19 C9
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set_io --warn-no-port pin20 E8
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set_io --warn-no-port pin21 A9
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set_io --warn-no-port pin22 A8
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set_io --warn-no-port pin23 A7
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set_io --warn-no-port pin24 A6
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