Apple-1-HW/verilog-apple-one
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Added synchronous reset to clk enable divider to avoid undefined logic state in simulation

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This commit is contained in:
Niels Moseley 2018-01-26 23:41:58 +01:00
parent cca11b7925
commit 9465e0c14d
2 changed files with 8 additions and 8 deletions
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12
iverilog/apple1_top_tb.v
View File

@ -25,7 +25,7 @@
module apple1_top_tb;
reg clk25, uart_rx;
reg clk25, uart_rx, rst_n;
wire uart_tx, uart_cts;
//////////////////////////////////////////////////////////////////////////
@ -33,7 +33,9 @@ module apple1_top_tb;
initial begin
clk25 = 1'b0;
uart_rx = 1'b0;
uart_rx = 1'b0;
rst_n = 1'b0;
#40 rst_n = 1'b1;
$display("Starting...");
$dumpfile("apple1_top_tb.vcd");
@ -48,15 +50,11 @@ module apple1_top_tb;
always
#20 clk25 = !clk25;
always
begin
#10000 $finish;
end
//////////////////////////////////////////////////////////////////////////
// Core of system
top core_top(
.clk25(clk25),
.rst_n(rst_n),
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts)

4
rtl/apple1_top.v
View File

@ -9,6 +9,8 @@
module top(
input clk25, // 25 MHz master clock
input rst_n, // active low synchronous reset (needed for simulation)
input uart_rx,
output uart_tx,
output uart_cts,
@ -51,7 +53,7 @@ module top(
reg [4:0] clk_div;
always @(posedge clk25)
begin
if (clk_div == 25)
if ((clk_div == 25) || (rst_n == 1'b0))
clk_div <= 0;
else
clk_div <= clk_div + 1'b1;