Added iverilog simulation support

iverilog/apple1_files.txt

@@ -0,0 +1,8 @@
+../rtl/cpu/ALU.v
+../rtl/cpu/cpu.v
+../rtl/uart/async_tx_rx.v
+../rtl/uart/uart.v
+../rtl/ram.v
+../rtl/rom_wozmon.v
+../rtl/apple1_top.v
+apple1_top_tb.v

iverilog/apple1_top_tb.v

@@ -0,0 +1,65 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Top level test bench for apple1_top
+//
+// Author.....: Niels A. Moseley
+// Date.......: 26-1-2018
+// 
+
+`timescale 1ns/1ps
+
+module apple1_top_tb;
+
+    reg clk25, uart_rx;
+    wire uart_tx, uart_cts;
+
+    //////////////////////////////////////////////////////////////////////////    
+    // Setup dumping of data for inspection
+
+    initial begin
+        clk25 = 1'b0;
+        uart_rx = 1'b0;  
+
+        $display("Starting...");
+        $dumpfile("apple1_top_tb.vcd");
+        $dumpvars;                
+        #1000000 $display("Stopping...");
+        $finish;
+    end
+
+    //////////////////////////////////////////////////////////////////////////    
+    // Clock
+
+    always
+        #20 clk25 = !clk25;
+
+    always 
+    begin
+        #10000 $finish;
+    end
+
+    //////////////////////////////////////////////////////////////////////////    
+    // Core of system
+    top core_top(
+        .clk25(clk25),
+        .uart_rx(uart_rx),
+        .uart_tx(uart_tx),
+        .uart_cts(uart_cts)
+    );
+
+endmodule

iverilog/run_testbench.bat

@@ -0,0 +1,2 @@
+iverilog -g2005 -s apple1_top_tb -o apple1_top_tb -c apple1_files.txt
+vvp apple1_top_tb

rtl/ram.v

@@ -10,7 +10,7 @@ module ram(
     reg [7:0] ram[0:8191];
 
     initial
-        $readmemh("../../../roms/ram.hex", ram, 0, 8191);
+        $readmemh("../roms/ram.hex", ram, 0, 8191);
 
     always @(posedge clk)
     begin

rtl/rom_wozmon.v

@@ -7,7 +7,7 @@ module rom_wozmon(
     reg [7:0] rom[0:255];
 
     initial
-        $readmemh("../../../roms/rom.hex", rom, 0, 255);
+        $readmemh("../roms/rom.hex", rom, 0, 255);
 
     always @(posedge clk)
     begin