added initial test of tinyfpga bx
This commit is contained in:
Alan Garfield
parent
6df00e7161
commit
99fc3e6ef5
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## System Clock
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set_io clk B2
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## VGA Display
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set_io vga_red A6
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set_io vga_grn B6
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set_io vga_blu A7
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set_io vga_h_sync B7
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set_io vga_v_sync A8
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## UART
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set_io uart_tx B1
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set_io uart_rx C2
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## Lighthouse
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set_io lt_dat H1
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set_io lt_env J1
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DEVICE = 8k
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PACKAGE = cm81
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FREQ_OSC = 16
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FREQ_PLL = 25
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PIN_DEF=tinyfpga_bx.pcf
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SOURCEDIR = ../../../rtl
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BUILDDIR = build
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PLL = $(BUILDDIR)/pll.sv
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all: apple1 prog
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info:
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@echo " To build: make apple1"
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@echo " To program: make prog"
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@echo "To build report: make report"
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@echo " To clean up: make clean"
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dir:
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mkdir -p $(BUILDDIR)
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
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yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^
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$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
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arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -mtr $@ $<
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%_tb.vvp: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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$(PLL):
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icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
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$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/clock.v \
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$(SOURCEDIR)/pwr_reset.v \
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$(SOURCEDIR)/ram.v \
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$(SOURCEDIR)/rom_wozmon.v \
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$(SOURCEDIR)/rom_basic.v \
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$(SOURCEDIR)/cpu/arlet_6502.v \
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$(SOURCEDIR)/cpu/arlet/ALU.v \
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$(SOURCEDIR)/cpu/arlet/cpu.v \
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$(SOURCEDIR)/uart/uart.v \
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$(SOURCEDIR)/uart/async_tx_rx.v \
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$(SOURCEDIR)/vga/vga.v \
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$(SOURCEDIR)/vga/vram.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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$(SOURCEDIR)/boards/tinyfpga_bx/clock_pll.v \
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$(SOURCEDIR)/boards/tinyfpga_bx/apple1_hx8k.v \
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$(BUILDDIR)/pll.sv
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apple1.rpt: $(BUILDDIR)/apple1.asc
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prog: dir $(BUILDDIR)/apple1.bin
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tinyprog -p $(filter-out $<,$^)
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# ------ HELPERS ------
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clean:
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rm -rf build apple1.rpt
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.SECONDARY:
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.PHONY: all info clean prog iceprog
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@ -0,0 +1 @@
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../tinyfpga_bx.pcf
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@ -0,0 +1,107 @@
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Miodrag Milanovic
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// Date.......: 11-2-2018
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//
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module apple1_top #(
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parameter BASIC_FILENAME = "../../../roms/basic.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
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) (
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input clk, // 16 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output reg vga_red, // red VGA signal
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output reg vga_grn, // green VGA signal
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output reg vga_blu, // blue VGA signal
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inout lt_dat,
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inout lt_env
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);
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wire clk25;
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// 16MHz up to 25MHz
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clock_pll clock_pll_inst(
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.REFERENCECLK(clk),
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.PLLOUTGLOBAL(clk25),
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.RESET(1'b1)
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);
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reg lt_data_rw;
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wire lt_data_in, lt_data_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) lt_dat_io (
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.PACKAGE_PIN(lt_dat),
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.OUTPUT_ENABLE(lt_data_rw),
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.D_IN_0(lt_data_in),
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.D_OUT_0(lt_data_out)
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);
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reg lt_env_rw;
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wire lt_env_in, lt_env_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) lt_env_io (
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.PACKAGE_PIN(lt_env),
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.OUTPUT_ENABLE(lt_env_rw),
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.D_IN_0(lt_env_in),
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.D_OUT_0(lt_env_out)
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);
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// apple one main system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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//.ps2_clk(),
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//.ps2_din(),
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.ps2_select(1'b1),
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.uart_rx(uart_tx),
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.uart_tx(uart_rx),
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//.uart_cts(),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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.vga_grn(vga_grn),
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.vga_blu(vga_blu)
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//.pc_monitor(pc_monitor)
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);
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endmodule
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@ -0,0 +1,38 @@
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module clock_pll(REFERENCECLK,
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PLLOUTCORE,
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PLLOUTGLOBAL,
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RESET);
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input REFERENCECLK;
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input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
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output PLLOUTCORE;
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output PLLOUTGLOBAL;
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SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
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.PLLOUTCORE(PLLOUTCORE),
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.PLLOUTGLOBAL(PLLOUTGLOBAL),
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.EXTFEEDBACK(),
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.DYNAMICDELAY(),
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.RESETB(RESET),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(),
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.LOCK(),
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.SDI(),
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.SDO(),
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.SCLK());
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//\\ Fin=16, Fout=25;
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defparam clock_pll_inst.DIVR = 4'b0000;
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defparam clock_pll_inst.DIVF = 7'b0110001;
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defparam clock_pll_inst.DIVQ = 3'b101;
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defparam clock_pll_inst.FILTER_RANGE = 3'b001;
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defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
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defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
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defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
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defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
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endmodule
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