Apple-1-HW/verilog-apple-one
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Increased ram to 32kb

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This commit is contained in:
lawrie 2020-04-05 16:48:49 +01:00
parent 0f9b231dbd
commit a7c01443ae
5 changed files with 8 additions and 8 deletions
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2
boards/ulx3s/yosys/Makefile
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@ -24,7 +24,7 @@ $(BUILDDIR)/%.config: $(PIN_DEF) $(BUILDDIR)/%.json
nextpnr-ecp5 --${DEVICE} --package CABGA381 --freq 25 --textcfg $@ --json $(filter-out $<,$^) --lpf $<
$(BUILDDIR)/%.bit: $(BUILDDIR)/%.config
ecppack --idcode ${IDCODE} $^ $@
ecppack --compress --idcode ${IDCODE} $^ $@
%_tb.vvp: %_tb.v %.v
iverilog -o $@ $^

BIN
boards/ulx3s/yosys/apple1.bit Normal file
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2
boards/ulx3s/yosys/ulx3s_v20.lpf
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@ -9,7 +9,7 @@ FREQUENCY PORT "clk_25mhz" 25 MHZ;
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
# write to FLASH possible any time from JTAG:
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
#SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
# write to FLASH possible from user bitstream:
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;

4
rtl/apple1.v
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@ -103,7 +103,7 @@ module apple1 #(
//////////////////////////////////////////////////////////////////////////
// Address Decoding
wire ram_cs = (ab[15:14] == 2'b00); // 0x0000 -> 0x3FFF
wire ram_cs = (ab[15] == 1'b0); // 0x0000 -> 0x7FFF
// font mode, background and foreground colour
wire vga_mode_cs = (ab[15:2] == 14'b11000000000000); // 0xC000 -> 0xC003
@ -134,7 +134,7 @@ module apple1 #(
.RAM_FILENAME (RAM_FILENAME)
) my_ram(
.clk(clk25),
.address(ab[13:0]),
.address(ab[14:0]),
.w_en(we & ram_cs),
.din(dbo),
.dout(ram_dout)

8
rtl/ram.v
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@ -26,16 +26,16 @@ module ram #(
parameter RAM_FILENAME = "../../../roms/ram.hex"
) (
input clk, // clock signal
input [13:0] address, // address bus
input [14:0] address, // address bus
input w_en, // active high write enable strobe
input [7:0] din, // 8-bit data bus (input)
output reg [7:0] dout // 8-bit data bus (output)
);
reg [7:0] ram_data[0:16383];
reg [7:0] ram_data[0:32767];
initial
$readmemh(RAM_FILENAME, ram_data, 0, 8191);
//initial
// $readmemh(RAM_FILENAME, ram_data, 0, 8191);
always @(posedge clk)
begin