Apple-1-HW/verilog-apple-one
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added reset to cpu registers and made uart ignore first tx

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This commit is contained in:
Alan Garfield 2018-01-27 22:56:28 +11:00
parent bcaf9e6962
commit abba4eeee6
2 changed files with 19 additions and 6 deletions
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16
rtl/cpu/arlet/cpu.v
View File

@ -530,9 +530,19 @@ end
* the PCL. This is possible, because the S register itself is stored in
* the ALU during those cycles.
*/
always @(posedge clk)
if( write_register & RDY )
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
always @(posedge clk or posedge reset)
begin
if (reset)
begin
AXYS[SEL_A] <= 8'b0;
AXYS[SEL_X] <= 8'b0;
AXYS[SEL_Y] <= 8'b0;
AXYS[SEL_S] <= 8'b0;
end
else
if( write_register & RDY )
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
end
/*
* register select logic. This determines which of the A, X, Y or

9
rtl/uart/uart.v
View File

@ -23,7 +23,7 @@ module uart(
parameter Baud = 115200;
parameter Oversampling = 8;
reg uart_tx_stb;
reg uart_tx_stb, uart_tx_init;
reg [7:0] uart_tx_byte;
wire uart_tx_status;
@ -86,9 +86,10 @@ module uart(
begin
dout <= 8'd0;
uart_tx_init <= 0; // flag to ignore the DDR setup from Wozmon PIA call
uart_tx_stb <= 0;
uart_rx_ack <= 0;
uart_tx_byte <= 8'd0;
uart_rx_ack <= 0;
end
else
begin
@ -108,11 +109,13 @@ module uart(
begin
// Apple 1 terminal only uses 7 bits, MSB indicates
// terminal has ack'd RX
if (~uart_tx_status)
if (~uart_tx_status && uart_tx_init)
begin
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end
else
uart_tx_init <= 1;
end
end