more tidy up on bx
This commit is contained in:
Alan Garfield
parent
d6a31cfd0e
commit
aea51dc240
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[Project]
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ProjectVersion=2.0
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Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
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ProjectName=icecube2
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Vendor=SiliconBlue
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Synthesis=synplify
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ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
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ProjectCFiles=
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CurImplementation=icecube2_Implmnt
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Implementations=icecube2_Implmnt
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StartFromSynthesis=yes
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IPGeneration=false
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[icecube2_Implmnt]
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DeviceFamily=iCE40
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Device=LP8K
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DevicePackage=CM81
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DevicePower=
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NetlistFile=icecube2_Implmnt/icecube2.edf
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AdditionalEDIFFile=
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IPEDIFFile=
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DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
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DesignView=_rt
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DesignCell=apple1_top
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SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
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UserPinConstraintFile=
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UserSDCFile=
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PhysicalConstraintFile=../tinyfpga_bx.pcf
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BackendImplPathName=
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Devicevoltage=1.14
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DevicevoltagePerformance=+/-5%(datasheet default)
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DeviceTemperature=85
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TimingAnalysisBasedOn=Worst
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OperationRange=Commercial
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TypicalCustomTemperature=25
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WorstCustomTemperature=85
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BestCustomTemperature=0
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IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
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derValue=1.03369
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TimingPathNumberStick=0
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[lse options]
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CarryChain=True
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CarryChainLength=0
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CommandLineOptions=
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EBRUtilization=100.00
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FSMEncodingStyle=Auto
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FixGatedClocks=True
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I/OInsertion=True
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IntermediateFileDump=False
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LoopLimit=1950
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MaximalFanout=10000
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MemoryInitialValueFileSearchPath=
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NumberOfCriticalPaths=3
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OptimizationGoal=Area
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PropagateConstants=True
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RAMStyle=Auto
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ROMStyle=Auto
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RWCheckOnRam=False
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RemoveDuplicateRegisters=True
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ResolvedMixedDrivers=False
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ResourceSharing=True
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TargetFrequency=
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TopLevelUnit=
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UseIORegister=Auto
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VHDL2008=False
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VerilogIncludeSearchPath=
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[tool options]
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PlacerEffortLevel=std
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PlacerAutoLutCascade=yes
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PlacerAutoRamCascade=yes
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PlacerPowerDriven=no
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PlacerAreaDriven=no
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RouteWithTimingDriven=yes
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RouteWithPinPermutation=yes
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BitmapSPIFlashMode=yes
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BitmapRAM4KInit=yes
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BitmapInitRamBank=1111
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BitmapOscillatorFR=low
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BitmapEnableWarmBoot=yes
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BitmapDisableHeader=no
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BitmapSetSecurity=no
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BitmapSetNoUsedIONoPullup=no
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FloorPlannerShowFanInNets=yes
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FloorPlannerShowFanOutNets=yes
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HookTo3rdPartyTextEditor=
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@ -0,0 +1,73 @@
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#-- Synopsys, Inc.
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#-- Project file Z:\boards\tinyfpga_bx\\icecube2\icecube2_syn.prj
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#project files
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add_file -verilog -lib work "../../../../rtl/apple1.v"
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add_file -verilog -lib work "../../../../rtl/clock.v"
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add_file -verilog -lib work "../../../../rtl/pwr_reset.v"
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add_file -verilog -lib work "../../../../rtl/ram.v"
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add_file -verilog -lib work "../../../../rtl/rom_basic.v"
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add_file -verilog -lib work "../../../../rtl/rom_wozmon.v"
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add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v"
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add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/clock_pll.v"
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add_file -verilog -lib work "../../../../rtl/cpu/arlet_6502.v"
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add_file -verilog -lib work "../../../../rtl/cpu/arlet/ALU.v"
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add_file -verilog -lib work "../../../../rtl/cpu/arlet/cpu.v"
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add_file -verilog -lib work "../../../../rtl/ps2keyboard/debounce.v"
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add_file -verilog -lib work "../../../../rtl/ps2keyboard/ps2keyboard.v"
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add_file -verilog -lib work "../../../../rtl/uart/async_tx_rx.v"
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add_file -verilog -lib work "../../../../rtl/uart/uart.v"
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add_file -verilog -lib work "../../../../rtl/vga/font_rom.v"
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add_file -verilog -lib work "../../../../rtl/vga/vga.v"
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add_file -verilog -lib work "../../../../rtl/vga/vram.v"
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#implementation: "icecube2_Implmnt"
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impl -add icecube2_Implmnt -type fpga
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#device options
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set_option -technology SBTiCE40
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set_option -part iCE40LP8K
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set_option -package CM81
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set_option -speed_grade
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set_option -part_companion ""
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#compilation/mapping options
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# mapper_options
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set_option -frequency auto
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set_option -write_verilog 0
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set_option -write_vhdl 0
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# Silicon Blue iCE40
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set_option -maxfan 10000
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set_option -disable_io_insertion 0
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set_option -pipe 1
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set_option -retiming 0
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set_option -update_models_cp 0
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set_option -fixgatedclocks 2
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set_option -fixgeneratedclocks 0
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# NFilter
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set_option -popfeed 0
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set_option -constprop 0
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set_option -createhierarchy 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_format "edif"
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project -result_file ./icecube2_Implmnt/icecube2.edf
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project -log_file "./icecube2_Implmnt/icecube2.srr"
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impl -active "icecube2_Implmnt"
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project -run synthesis -clean
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@ -177,7 +177,7 @@ module apple1 #(
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.address(ab[1:0]), // for uart
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.address(ab[1:0]),
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.w_en(we & uart_cs),
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.din(dbo),
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.dout(uart_dout)
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@ -56,7 +56,7 @@ module apple1_top #(
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);
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// lighthouse sensor
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reg lt_data_rw;
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wire lt_data_rw;
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wire lt_data_in, lt_data_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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@ -68,7 +68,7 @@ module apple1_top #(
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.D_OUT_0(lt_data_out)
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);
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reg lt_env_rw;
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wire lt_env_rw;
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wire lt_env_in, lt_env_out;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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@ -98,12 +98,11 @@ module apple1_top #(
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) my_apple1(
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.clk25(clk25),
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.rst_n(1'b1),
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.ps2_select(1'b0),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.ps2_clk(1'b0),
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.ps2_din(1'b0),
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.ps2_select(1'b0),
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.ps2_select(1'b1),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_red),
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@ -11,15 +11,15 @@ output PLLOUTGLOBAL;
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SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
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.PLLOUTCORE(PLLOUTCORE),
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.PLLOUTGLOBAL(PLLOUTGLOBAL),
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.EXTFEEDBACK(),
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.DYNAMICDELAY(),
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.EXTFEEDBACK(1'd0),
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.DYNAMICDELAY(8'd0),
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.RESETB(RESET),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(),
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.LATCHINPUTVALUE(1'd0),
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.LOCK(),
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.SDI(),
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.SDI(1'd0),
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.SDO(),
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.SCLK());
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.SCLK(1'd0));
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//\\ Fin=16, Fout=25;
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defparam clock_pll_inst.DIVR = 4'b0000;
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