Apple-1-HW/verilog-apple-one
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Fixed paths on upduino build

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This commit is contained in:
Alan Garfield 2018-02-12 09:35:44 +11:00
parent 54344e1203
commit b0d0d778f0
2 changed files with 11 additions and 13 deletions
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4
boards/upduino/yosys/Makefile
View File

@ -6,7 +6,7 @@ FREQ_PLL = 25
PIN_DEF=ice40up5k.pcf
SOURCEDIR = ../../rtl
SOURCEDIR = ../../../rtl
BUILDDIR = build
PLL=$(BUILDDIR)/pll.sv
@ -66,7 +66,7 @@ $(BUILDDIR)/apple1.blif: $(BUILDDIR)/pll.sv \
$(SOURCEDIR)/vga/font_rom.v \
$(SOURCEDIR)/ps2keyboard/debounce.v \
$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
$(SOURCEDIR)/boards/ice40up5k/apple1_up5k.v
$(SOURCEDIR)/boards/upduino/apple1_up5k.v
apple1.rpt: $(BUILDDIR)/apple1.asc

20
rtl/boards/upduino/apple1_up5k.v
View File

@ -49,18 +49,16 @@ module apple1_top(
wire clk25;
wire clk;
wire clk25;
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(clk)
);
pll pll(
.clock_in(clk),
.clock_out(clk25),
);
SB_HFOSC inthosc (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(clk)
);
pll pll(
.clock_in(clk),
.clock_out(clk25),
);
// apple one main system
apple1 my_apple1(