Apple-1-HW/verilog-apple-one
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fiddled project files from icecube

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This commit is contained in:
Alan Garfield 2018-01-28 00:19:59 +11:00
parent abba4eeee6
commit b42567e759
3 changed files with 7 additions and 7 deletions
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6
boards/ice40hx8k/appleone.xcf
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@ -19,13 +19,14 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>C:/Users/Alan/Documents/GitHub/apple-one/boards/ice40hx8k/appleone/appleone_Implmnt/sbt/outputs/bitmap/top_bitmap.bin</File>
<FileTime>01/26/18 18:17:10</FileTime>
<File>C:/Users/Alan/Documents/GitHub/apple-one/boards/ice40hx8k/appleone_Implmnt/sbt/outputs/bitmap/apple1_top_bitmap.bin</File>
<FileTime>01/27/18 23:59:33</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<TCKFrequency>1.000000 MHz</TCKFrequency>
<SVFProcessor>SVF Processor</SVFProcessor>
<AccessMode>CRAM</AccessMode>
</Option>
</Device>
@ -45,7 +46,6 @@
<PortAdd>FTUSB-0</PortAdd>
<USBID>Lattice FTUSB Interface Cable A Location 0000 Serial A</USBID>
<JTAGPinSetting>
TRST ABSENT;
ISPEN ABSENT;
</JTAGPinSetting>
</CableOptions>

6
boards/ice40hx8k/appleone_sbt.project
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@ -19,9 +19,9 @@ DevicePower=
NetlistFile=appleone_Implmnt/appleone.edf
AdditionalEDIFFile=
IPEDIFFile=
DesignLib=
DesignView=
DesignCell=
DesignLib=appleone_Implmnt/sbt/netlist/oadb-apple1_top
DesignView=_ep
DesignCell=apple1_top
SynthesisSDCFile=appleone_Implmnt/appleone.scf
UserPinConstraintFile=
UserSDCFile=

2
boards/ice40hx8k/appleone_syn.prd
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@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version L-2016.09L+ice40
#-- Project file C:\Users\Alan\Documents\GitHub\apple-one\boards\ice40hx8k\appleone_syn.prd
#-- Written on Sat Jan 27 14:12:58 2018
#-- Written on Sun Jan 28 00:17:28 2018
#
### Watch Implementation type ###