Apple-1-HW
/
verilog-apple-one
mirror of https://github.com/alangarf/apple-one.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

S3E updates.

This commit is contained in:
Niels Moseley 2018-02-12 16:47:52 +01:00
parent 3f8d13757b
commit f525631760
2 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
boards/spartan3e_starterkit/webpack_ise/Apple-One.gise
View File

@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1518447977" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518447958">
<transform xil_pn:end_ts="1518449446" xil_pn:in_ck="-2402892782883100176" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8720043281624233679" xil_pn:start_ts="1518449425">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -125,18 +125,22 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1518447982" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518447977">
<transform xil_pn:end_ts="1518449451" xil_pn:in_ck="-3894786652928293112" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-581701490373080307" xil_pn:start_ts="1518449446">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.bld"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.ngd"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1518447986" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518447982">
<transform xil_pn:end_ts="1518449456" xil_pn:in_ck="8375880660293788329" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1518449451">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.pcf"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_map.map"/>
@ -147,7 +151,7 @@
<outfile xil_pn:name="apple1_s3e_starterkit_top_summary.xml"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518447986">
<transform xil_pn:end_ts="1518449473" xil_pn:in_ck="-3296291810439397278" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1518449456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -161,9 +165,11 @@
<outfile xil_pn:name="apple1_s3e_starterkit_top_pad.txt"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1518448066" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518448055">
<transform xil_pn:end_ts="1518449484" xil_pn:in_ck="-5976217886481471090" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1518449473">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.bgn"/>
<outfile xil_pn:name="apple1_s3e_starterkit_top.bit"/>
@ -173,13 +179,11 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1518446623" xil_pn:in_ck="-5976217886481483944" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1518446622">
<transform xil_pn:end_ts="1518449494" xil_pn:in_ck="-5976217886481483944" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1518449489">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1518448003" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518447999">
<transform xil_pn:end_ts="1518449473" xil_pn:in_ck="-6485470272289971291" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1518449469">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

6
rtl/boards/spartan3e_starterkit/apple1_s3e_starterkit_top.v
View File

@ -24,11 +24,11 @@
module apple1_s3e_starterkit_top #(
parameter BASIC_FILENAME = "../../../roms/basic_ise.hex",
parameter BASIC_FILENAME = "../../../roms/basic.hex",
parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
parameter RAM_FILENAME = "../../../roms/ram_ise.hex",
parameter RAM_FILENAME = "../../../roms/ram.hex",
parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon_ise.hex"
parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
) (
input CLK_50MHZ, // the 50 MHz master clock