Apple-1-HW/verilog-apple-one
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Fixed address lines of Basic ROM

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This commit is contained in:
Niels Moseley 2018-01-28 20:18:56 +01:00
parent 1cea5d878f
commit fe05766894
4 changed files with 10 additions and 3 deletions
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1
boards/terasic_de0/apple-one.qsf
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@ -361,6 +361,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name VERILOG_FILE ../../rtl/rom_basic.v
set_global_assignment -name VERILOG_FILE ../../rtl/ps2keyboard/ps2keyboard.v
set_global_assignment -name VERILOG_FILE ../../rtl/boards/terasic_de0/segmentdisplay.v
set_global_assignment -name VERILOG_FILE ../../rtl/cpu/arlet/cpu.v

2
rtl/apple1.v
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@ -134,7 +134,7 @@ module apple1(
wire [7:0] basic_dout;
rom_basic #(BASIC_FILENAME) my_rom_basic (
.clk(clk25),
.address(ab[7:0]),
.address(ab[11:0]),
.dout(basic_dout)
);

4
rtl/rom_basic.v
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@ -1,12 +1,12 @@
module rom_basic(
input clk,
input [7:0] address,
input [11:0] address,
output reg [7:0] dout
);
parameter ROM_FILENAME = "../roms/basic.hex";
reg [7:0] rom[0:4095];
reg [11:0] rom[0:4095];
initial
$readmemh(ROM_FILENAME, rom, 0, 4095);

6
rtl/uart/uart.v
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@ -115,6 +115,12 @@ module uart(
// This causes the UART to ignore the very first byte sent.
if (~uart_tx_status && uart_tx_init)
begin
`ifdef SIM
if ((din & 8'h7f) >= 32)
$write("%c", din & 8'h7f);
`endif
uart_tx_byte <= {1'b0, din[6:0]};
uart_tx_stb <= 1;
end