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18 lines
300 B
Verilog
18 lines
300 B
Verilog
module rom_basic(
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input clk,
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input [11:0] address,
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output reg [7:0] dout
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);
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parameter ROM_FILENAME = "../roms/basic.hex";
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reg [11:0] rom[0:4095];
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initial
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$readmemh(ROM_FILENAME, rom, 0, 4095);
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always @(posedge clk)
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dout <= rom[address];
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endmodule
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