Apple-1-HW/verilog-apple-one
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41 Commits 3 Branches 0 Tags 6.9 MiB
0fc84e0b37
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3 Commits

Author SHA1 Message Date
Alan Garfield
0fc84e0b37 added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
Alan Garfield
abba4eeee6 added reset to cpu registers and made uart ignore first tx 2018-01-27 22:56:28 +11:00
Alan Garfield
c4d42fae3c fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00