Apple-1-HW/verilog-apple-one
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2226afe669
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3 Commits

Author SHA1 Message Date
Olof Kindgren
2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
 2018-02-12 14:04:00 +01:00
Alan Garfield
b0d0d778f0 Fixed paths on upduino build 2018-02-12 09:35:44 +11:00
Alan Garfield
ffad5968b6 moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00