Apple-1-HW
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verilog-apple-one
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verilog-apple-one/tools/iverilog
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Alan Garfield ea220fb9ab added uart testbench to look at cts signal 2018-02-16 13:40:46 +11:00
..
apple1_files.txt Moved test benches to tools 2018-02-12 07:02:41 +11:00
apple1_tb.v Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
run_testbench.bat Moved test benches to tools 2018-02-12 07:02:41 +11:00
run_uart_tb.sh added uart testbench to look at cts signal 2018-02-16 13:40:46 +11:00
run_vga_tb.sh Moved test benches to tools 2018-02-12 07:02:41 +11:00
uart_files.txt added uart testbench to look at cts signal 2018-02-16 13:40:46 +11:00
uart_tb.v added uart testbench to look at cts signal 2018-02-16 13:40:46 +11:00
vga_files.txt Moved test benches to tools 2018-02-12 07:02:41 +11:00
vga_tb.v Remove non-existing port assignments 2018-02-12 15:19:40 +01:00