Apple-1-HW/verilog-apple-one
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verilog-apple-one/boards/terasic_de0
History
Niels Moseley dd2c480675 Fixed reg/wire problems for Quartus.
2018-02-07 17:12:27 +01:00
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apple-one.pin Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
apple-one.qpf Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
apple-one.qsf Fixed reg/wire problems for Quartus. 2018-02-07 17:12:27 +01:00
apple-one.sdc Adding missing DE0 timing constraints file 2018-01-27 23:02:05 +01:00