mirror of
https://github.com/alangarf/apple-one.git
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91 lines
2.8 KiB
Verilog
91 lines
2.8 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level Apple 1 module for Digilent Spartan 3E
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// starter kit board
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//
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// Author.....: Niels A. Moseley
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// Date.......: 11-2-2018
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//
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module apple1_s3e_starterkit_top #(
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parameter BASIC_FILENAME = "../../../roms/basic_ise.hex",
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parameter FONT_ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex",
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parameter RAM_FILENAME = "../../../roms/ram_ise.hex",
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parameter VRAM_FILENAME = "../../../roms/vga_vram.bin",
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parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon_ise.hex"
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) (
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input CLK_50MHZ, // the 50 MHz master clock
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// UART I/O signals
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output UART_TXD, // UART transmit pin on board
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input UART_RXD, // UART receive pin on board
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input PS2_KBCLK,
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input PS2_KBDAT,
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input BUTTON,
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output VGA_R,
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output VGA_G,
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output VGA_B,
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output VGA_HS,
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output VGA_VS
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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reg clk25;
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wire [15:0] pc_monitor;
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wire rst_n;
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assign rst_n = ~BUTTON;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge CLK_50MHZ)
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begin
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clk25 <= ~clk25;
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end
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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apple1 #(
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.BASIC_FILENAME (BASIC_FILENAME),
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.FONT_ROM_FILENAME (FONT_ROM_FILENAME),
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.RAM_FILENAME (RAM_FILENAME),
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.VRAM_FILENAME (VRAM_FILENAME),
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.WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
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) apple1_top(
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.clk25(clk25),
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.rst_n(rst_n), // we don't have any reset pulse..
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.uart_rx(UART_RXD),
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.uart_tx(UART_TXD),
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//.uart_cts(UART_CTS), // there is no CTS on the board :(
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.ps2_clk(PS2_KBCLK),
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.ps2_din(PS2_KBDAT),
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.ps2_select(1'b1),
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.vga_h_sync(VGA_HS),
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.vga_v_sync(VGA_VS),
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.vga_red(VGA_R),
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.vga_grn(VGA_G),
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.vga_blu(VGA_B),
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.pc_monitor(pc_monitor)
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);
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endmodule
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