Apple-1-HW/verilog-apple-one
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abba4eeee6
verilog-apple-one/rtl/cpu
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Alan Garfield abba4eeee6 added reset to cpu registers and made uart ignore first tx
2018-01-27 22:56:28 +11:00
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aholme fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
arlet added reset to cpu registers and made uart ignore first tx 2018-01-27 22:56:28 +11:00
aholme_6502.v fixed testbench and split CPU cores 2018-01-27 17:00:33 +11:00
arlet_6502.v Yay got iverilog sim working! 2018-01-27 22:13:52 +11:00