mirror of
https://github.com/alangarf/apple-one.git
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65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level test bench for apple1_top
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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`timescale 1ns/1ps
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module apple1_top_tb;
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reg clk25, uart_rx;
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wire uart_tx, uart_cts;
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//////////////////////////////////////////////////////////////////////////
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// Setup dumping of data for inspection
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initial begin
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clk25 = 1'b0;
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uart_rx = 1'b0;
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$display("Starting...");
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$dumpfile("apple1_top_tb.vcd");
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$dumpvars;
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#1000000 $display("Stopping...");
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$finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Clock
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always
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#20 clk25 = !clk25;
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always
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begin
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#10000 $finish;
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end
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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top core_top(
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.clk25(clk25),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts)
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);
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endmodule |