Apple-1-HW/verilog-apple-one
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fe05766894
verilog-apple-one/rtl/uart
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Niels Moseley fe05766894 Fixed address lines of Basic ROM
2018-01-28 20:18:56 +01:00
..
async_tx_rx.v added reset logic to uart and CPU 2018-01-28 00:23:09 +11:00
uart.v Fixed address lines of Basic ROM 2018-01-28 20:18:56 +01:00