Apple-2-HW/Apple-II-Gate-Level-Xilinx-ISE-14.7-Schematic-Entry
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<bindings/>
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940
AppleIIGateSch/ClockVideoGenerator.sch Normal file
View File

@ -0,0 +1,940 @@
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<branch name="XLXN_13">
<wire x2="1072" y1="992" y2="992" x1="1040" />
</branch>
<instance x="1200" y="1056" name="XLXI_8" orien="R270" />
<branch name="XLXN_14">
<wire x2="1072" y1="240" y2="240" x1="1040" />
</branch>
<instance x="1200" y="304" name="XLXI_10" orien="R270" />
<branch name="VA">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1504" type="branch" />
<wire x2="448" y1="1504" y2="1504" x1="400" />
<wire x2="480" y1="1504" y2="1504" x1="448" />
<wire x2="656" y1="1504" y2="1504" x1="480" />
<wire x2="1168" y1="1376" y2="1376" x1="480" />
<wire x2="1168" y1="1376" y2="1504" x1="1168" />
<wire x2="480" y1="1376" y2="1504" x1="480" />
<wire x2="1168" y1="1504" y2="1504" x1="1040" />
</branch>
<branch name="XLXN_17">
<wire x2="1312" y1="432" y2="432" x1="1040" />
<wire x2="1312" y1="432" y2="864" x1="1312" />
<wire x2="1312" y1="864" y2="1056" x1="1312" />
<wire x2="1312" y1="864" y2="864" x1="1040" />
<wire x2="1312" y1="1056" y2="1056" x1="1040" />
</branch>
<branch name="V5">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="240" type="branch" />
<wire x2="448" y1="240" y2="240" x1="368" />
<wire x2="656" y1="240" y2="240" x1="448" />
</branch>
<branch name="V4">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="304" type="branch" />
<wire x2="448" y1="304" y2="304" x1="368" />
<wire x2="656" y1="304" y2="304" x1="448" />
</branch>
<branch name="V3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="368" type="branch" />
<wire x2="448" y1="368" y2="368" x1="368" />
<wire x2="656" y1="368" y2="368" x1="448" />
</branch>
<branch name="V2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="432" type="branch" />
<wire x2="448" y1="432" y2="432" x1="368" />
<wire x2="656" y1="432" y2="432" x1="448" />
</branch>
<branch name="V1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="864" type="branch" />
<wire x2="448" y1="864" y2="864" x1="400" />
<wire x2="656" y1="864" y2="864" x1="448" />
</branch>
<branch name="V0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="928" type="branch" />
<wire x2="448" y1="928" y2="928" x1="400" />
<wire x2="656" y1="928" y2="928" x1="448" />
</branch>
<branch name="VC">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="992" type="branch" />
<wire x2="448" y1="992" y2="992" x1="400" />
<wire x2="656" y1="992" y2="992" x1="448" />
</branch>
<branch name="VB">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1056" type="branch" />
<wire x2="448" y1="1056" y2="1056" x1="400" />
<wire x2="656" y1="1056" y2="1056" x1="448" />
</branch>
<branch name="H5">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1632" type="branch" />
<wire x2="448" y1="1632" y2="1632" x1="400" />
<wire x2="656" y1="1632" y2="1632" x1="448" />
</branch>
<branch name="H4">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="1696" type="branch" />
<wire x2="448" y1="1696" y2="1696" x1="400" />
<wire x2="656" y1="1696" y2="1696" x1="448" />
</branch>
<branch name="H3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2144" type="branch" />
<wire x2="448" y1="2144" y2="2144" x1="400" />
<wire x2="656" y1="2144" y2="2144" x1="448" />
</branch>
<branch name="H2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2208" type="branch" />
<wire x2="448" y1="2208" y2="2208" x1="400" />
<wire x2="656" y1="2208" y2="2208" x1="448" />
</branch>
<branch name="H1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2272" type="branch" />
<wire x2="448" y1="2272" y2="2272" x1="400" />
<wire x2="656" y1="2272" y2="2272" x1="448" />
</branch>
<branch name="H0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2336" type="branch" />
<wire x2="448" y1="2336" y2="2336" x1="400" />
<wire x2="656" y1="2336" y2="2336" x1="448" />
</branch>
<iomarker fontsize="28" x="368" y="240" name="V5" orien="R180" />
<iomarker fontsize="28" x="368" y="304" name="V4" orien="R180" />
<iomarker fontsize="28" x="368" y="368" name="V3" orien="R180" />
<iomarker fontsize="28" x="368" y="432" name="V2" orien="R180" />
<iomarker fontsize="28" x="400" y="864" name="V1" orien="R180" />
<iomarker fontsize="28" x="400" y="928" name="V0" orien="R180" />
<iomarker fontsize="28" x="400" y="992" name="VC" orien="R180" />
<iomarker fontsize="28" x="400" y="1056" name="VB" orien="R180" />
<iomarker fontsize="28" x="400" y="1504" name="VA" orien="R180" />
<iomarker fontsize="28" x="400" y="1632" name="H5" orien="R180" />
<iomarker fontsize="28" x="400" y="1696" name="H4" orien="R180" />
<iomarker fontsize="28" x="400" y="2144" name="H3" orien="R180" />
<iomarker fontsize="28" x="400" y="2208" name="H2" orien="R180" />
<iomarker fontsize="28" x="400" y="2272" name="H1" orien="R180" />
<iomarker fontsize="28" x="400" y="2336" name="H0" orien="R180" />
<branch name="SOFT5_A2_11">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="2464" type="branch" />
<wire x2="448" y1="2464" y2="2464" x1="384" />
<wire x2="512" y1="2464" y2="2464" x1="448" />
<wire x2="656" y1="2464" y2="2464" x1="512" />
<wire x2="512" y1="2464" y2="2592" x1="512" />
<wire x2="624" y1="2592" y2="2592" x1="512" />
<wire x2="1072" y1="2592" y2="2592" x1="624" />
<wire x2="1072" y1="2592" y2="2608" x1="1072" />
<wire x2="1312" y1="2608" y2="2608" x1="1072" />
<wire x2="656" y1="560" y2="560" x1="512" />
<wire x2="512" y1="560" y2="1184" x1="512" />
<wire x2="512" y1="1184" y2="1824" x1="512" />
<wire x2="512" y1="1824" y2="2464" x1="512" />
<wire x2="656" y1="1824" y2="1824" x1="512" />
<wire x2="656" y1="1184" y2="1184" x1="512" />
<wire x2="656" y1="2528" y2="2528" x1="624" />
<wire x2="624" y1="2528" y2="2592" x1="624" />
<wire x2="1312" y1="1568" y2="1568" x1="1040" />
<wire x2="1312" y1="1568" y2="2608" x1="1312" />
<wire x2="1072" y1="2528" y2="2528" x1="1040" />
<wire x2="1072" y1="2528" y2="2592" x1="1072" />
</branch>
<instance x="1248" y="432" name="XLXI_12" orien="R0" />
<text style="fontsize:28;fontname:Arial" x="1196" y="396">NTSC=1 PAL=0</text>
<branch name="SOFT5_A2_8">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1376" y="2192" type="branch" />
<wire x2="1376" y1="704" y2="1248" x1="1376" />
<wire x2="1376" y1="1248" y2="2080" x1="1376" />
<wire x2="1376" y1="2080" y2="2192" x1="1376" />
<wire x2="1376" y1="2192" y2="2288" x1="1376" />
<wire x2="2304" y1="2080" y2="2080" x1="1376" />
<wire x2="2736" y1="1248" y2="1248" x1="1376" />
<wire x2="2736" y1="960" y2="960" x1="2688" />
<wire x2="2736" y1="960" y2="1248" x1="2736" />
</branch>
<instance x="1856" y="864" name="D2_1of4_74LS20" orien="R0">
<attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="16" y="-80" type="instance" />
</instance>
<branch name="XLXN_35">
<wire x2="1856" y1="672" y2="672" x1="1632" />
</branch>
<instance x="2304" y="1056" name="XLXI_15" orien="R0">
</instance>
<branch name="XLXN_36">
<wire x2="2304" y1="704" y2="704" x1="2112" />
</branch>
<instance x="1792" y="544" name="B12_2of4_74LS11" orien="R270">
<attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="224" y="-368" type="instance" />
</instance>
<instance x="1904" y="400" name="A2_1of4_74LS08" orien="R270">
<attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="144" y="-32" type="instance" />
</instance>
<branch name="RASn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="832" type="branch" />
<wire x2="2240" y1="496" y2="576" x1="2240" />
<wire x2="2304" y1="576" y2="576" x1="2240" />
<wire x2="2736" y1="496" y2="496" x1="2240" />
<wire x2="2736" y1="496" y2="832" x1="2736" />
<wire x2="3056" y1="832" y2="832" x1="2736" />
<wire x2="3120" y1="832" y2="832" x1="3056" />
<wire x2="2736" y1="832" y2="832" x1="2688" />
</branch>
<branch name="CASn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="704" type="branch" />
<wire x2="2832" y1="704" y2="704" x1="2688" />
<wire x2="3056" y1="704" y2="704" x1="2832" />
<wire x2="3120" y1="704" y2="704" x1="3056" />
<wire x2="2832" y1="448" y2="704" x1="2832" />
</branch>
<branch name="AX">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="768" type="branch" />
<wire x2="2768" y1="464" y2="464" x1="2192" />
<wire x2="2768" y1="464" y2="768" x1="2768" />
<wire x2="3056" y1="768" y2="768" x1="2768" />
<wire x2="3120" y1="768" y2="768" x1="3056" />
<wire x2="2192" y1="464" y2="640" x1="2192" />
<wire x2="2304" y1="640" y2="640" x1="2192" />
<wire x2="2192" y1="640" y2="768" x1="2192" />
<wire x2="2304" y1="768" y2="768" x1="2192" />
<wire x2="2192" y1="768" y2="1296" x1="2192" />
<wire x2="2304" y1="1296" y2="1296" x1="2192" />
<wire x2="2768" y1="768" y2="768" x1="2688" />
<wire x2="2768" y1="448" y2="464" x1="2768" />
</branch>
<instance x="2896" y="448" name="B13_3of4_74LS02" orien="R270">
<attrtext style="alignment:VRIGHT;fontsize:28;fontname:Arial" attrname="InstName" x="192" y="-368" type="instance" />
</instance>
<branch name="XLXN_44">
<wire x2="2304" y1="1024" y2="1072" x1="2304" />
<wire x2="2688" y1="1072" y2="1072" x1="2304" />
<wire x2="2688" y1="1072" y2="1104" x1="2688" />
<wire x2="2688" y1="1024" y2="1072" x1="2688" />
</branch>
<branch name="Q3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="640" type="branch" />
<wire x2="2304" y1="832" y2="832" x1="2256" />
<wire x2="2256" y1="832" y2="1104" x1="2256" />
<wire x2="2864" y1="1104" y2="1104" x1="2256" />
<wire x2="2864" y1="1104" y2="1488" x1="2864" />
<wire x2="2864" y1="640" y2="640" x1="2688" />
<wire x2="2864" y1="640" y2="1104" x1="2864" />
<wire x2="3056" y1="640" y2="640" x1="2864" />
<wire x2="3120" y1="640" y2="640" x1="3056" />
<wire x2="2864" y1="1488" y2="1488" x1="2688" />
</branch>
<instance x="2624" y="1232" name="XLXI_19" orien="R0" />
<branch name="XLXN_46">
<wire x2="1664" y1="544" y2="576" x1="1664" />
<wire x2="1840" y1="576" y2="576" x1="1664" />
<wire x2="1840" y1="576" y2="608" x1="1840" />
<wire x2="1856" y1="608" y2="608" x1="1840" />
<wire x2="1840" y1="400" y2="416" x1="1840" />
<wire x2="2368" y1="416" y2="416" x1="1840" />
<wire x2="1840" y1="416" y2="576" x1="1840" />
<wire x2="2368" y1="176" y2="416" x1="2368" />
<wire x2="2800" y1="176" y2="176" x1="2368" />
<wire x2="2800" y1="176" y2="192" x1="2800" />
</branch>
<iomarker fontsize="28" x="3120" y="640" name="Q3" orien="R0" />
<iomarker fontsize="28" x="3120" y="704" name="CASn" orien="R0" />
<iomarker fontsize="28" x="3120" y="768" name="AX" orien="R0" />
<iomarker fontsize="28" x="3120" y="832" name="RASn" orien="R0" />
<branch name="LDPSn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="448" y="48" type="branch" />
<wire x2="448" y1="48" y2="48" x1="368" />
<wire x2="1424" y1="48" y2="48" x1="448" />
<wire x2="1424" y1="48" y2="480" x1="1424" />
<wire x2="1808" y1="48" y2="48" x1="1424" />
<wire x2="1808" y1="48" y2="144" x1="1808" />
<wire x2="1344" y1="560" y2="560" x1="1040" />
<wire x2="1344" y1="560" y2="1184" x1="1344" />
<wire x2="1344" y1="1184" y2="1824" x1="1344" />
<wire x2="1344" y1="1824" y2="2464" x1="1344" />
<wire x2="1344" y1="1184" y2="1184" x1="1040" />
<wire x2="1344" y1="1824" y2="1824" x1="1040" />
<wire x2="1344" y1="2464" y2="2464" x1="1040" />
<wire x2="1344" y1="480" y2="560" x1="1344" />
<wire x2="1424" y1="480" y2="480" x1="1344" />
</branch>
<iomarker fontsize="28" x="368" y="48" name="LDPSn" orien="R180" />
<instance x="1376" y="768" name="B2_2of4_74S86" orien="R0">
<attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="32" y="0" type="instance" />
</instance>
<branch name="LD194">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1632" y="128" type="branch" />
<wire x2="1632" y1="128" y2="128" x1="1600" />
<wire x2="1664" y1="128" y2="128" x1="1632" />
<wire x2="1664" y1="128" y2="288" x1="1664" />
</branch>
<iomarker fontsize="28" x="1600" y="128" name="LD194" orien="R180" />
<branch name="XLXN_54">
<wire x2="2720" y1="576" y2="576" x1="2688" />
<wire x2="2720" y1="576" y2="1360" x1="2720" />
<wire x2="2720" y1="1360" y2="1360" x1="2688" />
</branch>
<branch name="XLXN_52">
<wire x2="2304" y1="1488" y2="1488" x1="2272" />
</branch>
<iomarker fontsize="28" x="3136" y="2080" name="PHI0" orien="R0" />
<branch name="COLOR_REF">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3040" y="2272" type="branch" />
<wire x2="3040" y1="2272" y2="2272" x1="2688" />
<wire x2="3136" y1="2272" y2="2272" x1="3040" />
</branch>
<iomarker fontsize="28" x="3136" y="2272" name="COLOR_REF" orien="R0" />
<instance x="2000" y="2368" name="B2_1of4_74S86" orien="R0">
<attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="-112" y="-160" type="instance" />
</instance>
<branch name="XLXN_64">
<wire x2="2304" y1="2272" y2="2272" x1="2256" />
</branch>
<branch name="c7M">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3072" y="2464" type="branch" />
<wire x2="2000" y1="2304" y2="2304" x1="1968" />
<wire x2="1968" y1="2304" y2="2560" x1="1968" />
<wire x2="2736" y1="2560" y2="2560" x1="1968" />
<wire x2="2736" y1="2464" y2="2464" x1="2688" />
<wire x2="2736" y1="2464" y2="2560" x1="2736" />
<wire x2="3072" y1="2464" y2="2464" x1="2736" />
<wire x2="3136" y1="2464" y2="2464" x1="3072" />
</branch>
<branch name="c7Mn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3072" y="2400" type="branch" />
<wire x2="1728" y1="544" y2="2528" x1="1728" />
<wire x2="2288" y1="2528" y2="2528" x1="1728" />
<wire x2="2704" y1="2528" y2="2528" x1="2288" />
<wire x2="2304" y1="2336" y2="2336" x1="2288" />
<wire x2="2288" y1="2336" y2="2528" x1="2288" />
<wire x2="2704" y1="2400" y2="2400" x1="2688" />
<wire x2="2704" y1="2400" y2="2528" x1="2704" />
<wire x2="3072" y1="2400" y2="2400" x1="2704" />
<wire x2="3136" y1="2400" y2="2400" x1="3072" />
</branch>
<instance x="2144" y="1424" name="XLXI_21" orien="R90" />
<branch name="XLXN_72">
<wire x2="2144" y1="1360" y2="2208" x1="2144" />
<wire x2="2304" y1="2208" y2="2208" x1="2144" />
<wire x2="2304" y1="1360" y2="1360" x1="2144" />
</branch>
<iomarker fontsize="28" x="3136" y="2400" name="c7Mn" orien="R0" />
<iomarker fontsize="28" x="3136" y="2464" name="c7M" orien="R0" />
<iomarker fontsize="28" x="1376" y="2288" name="SOFT5_A2_8" orien="R90" />
<instance x="272" y="2736" name="B2_3of4_74S86" orien="R0">
<attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="208" y="-64" type="instance" />
</instance>
<branch name="XLXN_76">
<wire x2="1936" y1="2640" y2="2640" x1="528" />
<wire x2="2304" y1="960" y2="960" x1="1936" />
<wire x2="1936" y1="960" y2="2016" x1="1936" />
<wire x2="1936" y1="2016" y2="2640" x1="1936" />
<wire x2="2304" y1="2016" y2="2016" x1="1936" />
</branch>
<branch name="CLK_14o3M">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="256" y="2608" type="branch" />
<wire x2="256" y1="2608" y2="2608" x1="192" />
<wire x2="272" y1="2608" y2="2608" x1="256" />
</branch>
<iomarker fontsize="28" x="192" y="2608" name="CLK_14o3M" orien="R180" />
<text style="fontsize:48;fontname:Arial" x="20" y="2524">14.31818 Mhz Clock</text>
<branch name="XLXN_78">
<wire x2="272" y1="2672" y2="2672" x1="240" />
</branch>
<instance x="112" y="2608" name="XLXI_25" orien="R90" />
<instance x="2304" y="1840" name="C1_74LS153" orien="R0">
<attrtext style="fontsize:28;fontname:Arial" attrname="InstName" x="-112" y="-512" type="instance" />
</instance>
<branch name="XLXN_79">
<wire x2="2304" y1="1552" y2="1552" x1="2272" />
</branch>
<instance x="2272" y="1616" name="XLXI_26" orien="R270" />
<branch name="XLXN_82">
<wire x2="2704" y1="1616" y2="1616" x1="2688" />
<wire x2="2704" y1="1616" y2="1680" x1="2704" />
<wire x2="2704" y1="1680" y2="1744" x1="2704" />
<wire x2="2704" y1="1744" y2="1808" x1="2704" />
<wire x2="2816" y1="1616" y2="1616" x1="2704" />
<wire x2="2704" y1="1680" y2="1680" x1="2688" />
<wire x2="2704" y1="1744" y2="1744" x1="2688" />
<wire x2="2704" y1="1808" y2="1808" x1="2688" />
</branch>
<instance x="2816" y="1552" name="XLXI_27" orien="R90" />
<text x="2776" y="1584">Temp.. NOT USED HERE. Don't want floating</text>
<branch name="PHI1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3024" y="2016" type="branch" />
<wire x2="3024" y1="2016" y2="2016" x1="2688" />
<wire x2="3136" y1="2016" y2="2016" x1="3024" />
</branch>
<instance x="2304" y="2496" name="XLXI_22" orien="R0">
</instance>
<branch name="XLXN_62">
<wire x2="2224" y1="1920" y2="2144" x1="2224" />
<wire x2="2304" y1="2144" y2="2144" x1="2224" />
<wire x2="2784" y1="1920" y2="1920" x1="2224" />
<wire x2="2784" y1="1920" y2="2208" x1="2784" />
<wire x2="2784" y1="1296" y2="1296" x1="2688" />
<wire x2="2784" y1="1296" y2="1424" x1="2784" />
<wire x2="2784" y1="1424" y2="1920" x1="2784" />
<wire x2="2784" y1="1424" y2="1424" x1="2688" />
<wire x2="2784" y1="2208" y2="2208" x1="2688" />
</branch>
<iomarker fontsize="28" x="3136" y="2016" name="PHI1" orien="R0" />
<branch name="PHI0">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1600" y="576" type="branch" />
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3056" y="2080" type="branch" />
<wire x2="1600" y1="544" y2="576" x1="1600" />
<wire x2="1600" y1="576" y2="608" x1="1600" />
<wire x2="1776" y1="608" y2="608" x1="1600" />
<wire x2="1776" y1="608" y2="736" x1="1776" />
<wire x2="1856" y1="736" y2="736" x1="1776" />
<wire x2="1776" y1="736" y2="1808" x1="1776" />
<wire x2="2288" y1="1808" y2="1808" x1="1776" />
<wire x2="2304" y1="1808" y2="1808" x1="2288" />
<wire x2="2288" y1="1808" y2="1872" x1="2288" />
<wire x2="2752" y1="1872" y2="1872" x1="2288" />
<wire x2="2752" y1="1872" y2="2080" x1="2752" />
<wire x2="3056" y1="2080" y2="2080" x1="2752" />
<wire x2="3136" y1="2080" y2="2080" x1="3056" />
<wire x2="1776" y1="400" y2="608" x1="1776" />
<wire x2="2752" y1="2080" y2="2080" x1="2688" />
</branch>
<branch name="XLXN_87">
<wire x2="1856" y1="800" y2="800" x1="1824" />
<wire x2="1824" y1="800" y2="2240" x1="1824" />
<wire x2="1824" y1="2240" y2="2544" x1="1824" />
<wire x2="2768" y1="2544" y2="2544" x1="1824" />
<wire x2="2000" y1="2240" y2="2240" x1="1824" />
<wire x2="2768" y1="2336" y2="2336" x1="2688" />
<wire x2="2768" y1="2336" y2="2544" x1="2768" />
</branch>
</sheet>
</drawing>

107
AppleIIGateSch/ClockVideoGenerator.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="ClockVideoGenerator">
<symboltype>BLOCK</symboltype>
<timestamp>2018-6-5T4:4:38</timestamp>
<pin polarity="Output" x="1120" y="-1472" name="AX" />
<pin polarity="Output" x="1184" y="-1472" name="CASn" />
<pin polarity="Output" x="1312" y="-1472" name="COLOR_REF" />
<pin polarity="Output" x="992" y="-1472" name="H0" />
<pin polarity="Output" x="928" y="-1472" name="H1" />
<pin polarity="Output" x="864" y="-1472" name="H2" />
<pin polarity="Output" x="800" y="-1472" name="H3" />
<pin polarity="Output" x="736" y="-1472" name="H4" />
<pin polarity="Output" x="672" y="-1472" name="H5" />
<pin polarity="Output" x="1376" y="-1472" name="LD194" />
<pin polarity="Output" x="1056" y="-1472" name="LDPSn" />
<pin polarity="Output" x="1248" y="-1472" name="RASn" />
<pin polarity="Input" x="96" y="0" name="SOFT5_A2_11" />
<pin polarity="Input" x="160" y="0" name="SOFT5_A2_8" />
<pin polarity="Output" x="416" y="-1472" name="V0" />
<pin polarity="Output" x="352" y="-1472" name="V1" />
<pin polarity="Output" x="288" y="-1472" name="V2" />
<pin polarity="Output" x="224" y="-1472" name="V3" />
<pin polarity="Output" x="160" y="-1472" name="V4" />
<pin polarity="Output" x="96" y="-1472" name="V5" />
<pin polarity="Output" x="608" y="-1472" name="VA" />
<pin polarity="Output" x="544" y="-1472" name="VB" />
<pin polarity="Output" x="480" y="-1472" name="VC" />
<pin polarity="Input" x="0" y="-592" name="CLK_14o3M" />
<pin polarity="Output" x="1472" y="-912" name="c7M" />
<pin polarity="Output" x="1472" y="-848" name="c7Mn" />
<pin polarity="Output" x="1472" y="-784" name="PHI0" />
<pin polarity="Output" x="1472" y="-720" name="PHI1" />
<pin polarity="Output" x="1472" y="-656" name="Q3" />
<graph>
<rect width="1344" x="64" y="-1408" height="1344" />
<attrtext style="alignment:CENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="736" y="-736" type="symbol" />
<line x2="1120" y1="-1408" y2="-1472" x1="1120" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1120" y="-1400" type="pin AX" />
<line x2="1184" y1="-1408" y2="-1472" x1="1184" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1184" y="-1400" type="pin CASn" />
<line x2="1312" y1="-1408" y2="-1472" x1="1312" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1312" y="-1400" type="pin COLOR_REF" />
<line x2="992" y1="-1408" y2="-1472" x1="992" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="992" y="-1400" type="pin H0" />
<line x2="928" y1="-1408" y2="-1472" x1="928" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="928" y="-1400" type="pin H1" />
<line x2="864" y1="-1408" y2="-1472" x1="864" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="864" y="-1400" type="pin H2" />
<line x2="800" y1="-1408" y2="-1472" x1="800" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="800" y="-1400" type="pin H3" />
<line x2="736" y1="-1408" y2="-1472" x1="736" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="736" y="-1400" type="pin H4" />
<line x2="672" y1="-1408" y2="-1472" x1="672" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="672" y="-1400" type="pin H5" />
<line x2="1376" y1="-1408" y2="-1472" x1="1376" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1376" y="-1400" type="pin LD194" />
<line x2="1056" y1="-1408" y2="-1472" x1="1056" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1056" y="-1400" type="pin LDPSn" />
<line x2="1248" y1="-1408" y2="-1472" x1="1248" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1248" y="-1400" type="pin RASn" />
<line x2="96" y1="-64" y2="0" x1="96" />
<attrtext style="alignment:VLEFT;fontsize:24;fontname:Arial" attrname="PinName" x="96" y="-72" type="pin SOFT5_A2_11" />
<line x2="160" y1="-64" y2="0" x1="160" />
<attrtext style="alignment:VLEFT;fontsize:24;fontname:Arial" attrname="PinName" x="160" y="-72" type="pin SOFT5_A2_8" />
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<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="416" y="-1400" type="pin V0" />
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<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="352" y="-1400" type="pin V1" />
<line x2="288" y1="-1408" y2="-1472" x1="288" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="288" y="-1400" type="pin V2" />
<line x2="224" y1="-1408" y2="-1472" x1="224" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="224" y="-1400" type="pin V3" />
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<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="608" y="-1400" type="pin VA" />
<line x2="544" y1="-1408" y2="-1472" x1="544" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="544" y="-1400" type="pin VB" />
<line x2="480" y1="-1408" y2="-1472" x1="480" />
<attrtext style="alignment:VRIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="480" y="-1400" type="pin VC" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="84" y="-592" type="pin CLK_14o3M" />
<line x2="0" y1="-592" y2="-592" x1="60" />
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<line x2="1472" y1="-848" y2="-848" x1="1408" />
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<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-656" type="pin Q3" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-720" type="pin PHI1" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-784" type="pin PHI0" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-848" type="pin c7Mn" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="1400" y="-912" type="pin c7M" />
<text style="fontsize:56;fontname:Arial" x="284" y="-1100">APPLE II Clock and Video Generator</text>
<text style="fontsize:44;fontname:Arial" x="492" y="-1028">Entered into Xilinx ISE 14.7</text>
<text style="fontsize:44;fontname:Arial" x="740" y="-976">by</text>
<text style="fontsize:40;fontname:Arial" x="636" y="-924">Frederick Kilner </text>
<text style="fontsize:32;fontname:Arial" x="504" y="-876">June 4th Year or our Lord 2018 A.D.</text>
<text style="fontsize:32;fontname:Arial" x="548" y="-112">Apple ][ Will Live Forever</text>
<circle r="12" cx="1056" cy="-1416" />
<circle r="12" cx="1186" cy="-1416" />
<circle r="12" cx="1246" cy="-1416" />
<circle r="10" cx="94" cy="-54" />
<circle r="11" cx="160" cy="-54" />
</graph>
</symbol>

3
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AppleIIGateSch/ClockVideoGenerator_isim_beh1.wdb Normal file
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>ClockVideoGenerator Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>AppleIIGateSch.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>ClockVideoGenerator</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s500e-4fg320</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Jun 7 00:01:13 2018</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 06/07/2018 - 15:05:13</center>
</BODY></HTML>

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AppleIIGateSch/ClockVideoGenerator_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\ClockVideoGenerator.sch - Sun Jun 03 21:54:27 2018
`timescale 1ns / 1ps
module ClockVideoGenerator_ClockVideoGenerator_sch_tb();
// Inputs
reg SOFT5_A2_11;
reg SOFT5_A2_8;
reg CLK_14o3M;
// Output
wire VA;
wire V5;
wire V4;
wire V3;
wire V2;
wire V1;
wire V0;
wire VC;
wire VB;
wire H5;
wire H4;
wire H3;
wire H2;
wire H1;
wire H0;
wire RASn;
wire CASn;
wire AX;
wire Q3;
wire LDPSn;
wire LD194;
wire PHI0;
wire PHI1;
wire COLOR_REF;
wire c7M;
wire c7Mn;
// Bidirs
// TB vars and stuff
integer i;
// Instantiate the UUT
ClockVideoGenerator UUT (
.SOFT5_A2_11(SOFT5_A2_11),
.V5(V5),
.V4(V4),
.V3(V3),
.V2(V2),
.V1(V1),
.V0(V0),
.VC(VC),
.VB(VB),
.VA(VA),
.H5(H5),
.H4(H4),
.H3(H3),
.H2(H2),
.H1(H1),
.H0(H0),
.SOFT5_A2_8(SOFT5_A2_8),
.RASn(RASn),
.CASn(CASn),
.AX(AX),
.Q3(Q3),
.LDPSn(LDPSn),
.LD194(LD194),
.PHI0(PHI0),
.PHI1(PHI1),
.COLOR_REF(COLOR_REF),
.c7M(c7M),
.c7Mn(c7Mn),
.CLK_14o3M(CLK_14o3M)
);
// Initialize Inputs
`ifdef auto_init
initial begin
$display("auto_init set");
end
`else
initial begin
$display("NOT SET auto_init");
end
`endif
initial begin
SOFT5_A2_11 = 0;
SOFT5_A2_8 = 0;
#5
SOFT5_A2_11 = 1;
SOFT5_A2_8 = 1;
#5
CLK_14o3M = 0;
#100
for (i=0; i<3000; i = i + 1) begin
CLK_14o3M = 0;
#5;
CLK_14o3M = 1;
#5;
end
$finish;
end
endmodule

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MODULE JK_FlipFlop

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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3e" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="Q" />
<signal name="Qnot" />
<signal name="XLXN_6" />
<signal name="XLXN_7" />
<signal name="CLK" />
<signal name="J" />
<signal name="K" />
<port polarity="Output" name="Q" />
<port polarity="Output" name="Qnot" />
<port polarity="Input" name="CLK" />
<port polarity="Input" name="J" />
<port polarity="Input" name="K" />
<blockdef name="nand2">
<timestamp>2000-1-1T10:10:10</timestamp>
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<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
</blockdef>
<blockdef name="nand3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="216" y1="-128" y2="-128" x1="256" />
<circle r="12" cx="204" cy="-128" />
<line x2="144" y1="-176" y2="-176" x1="64" />
<line x2="64" y1="-80" y2="-80" x1="144" />
<arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
<line x2="64" y1="-64" y2="-192" x1="64" />
</blockdef>
<block symbolname="nand2" name="XLXI_1">
<blockpin signalname="Qnot" name="I0" />
<blockpin signalname="XLXN_6" name="I1" />
<blockpin signalname="Q" name="O" />
</block>
<block symbolname="nand2" name="XLXI_2">
<blockpin signalname="XLXN_7" name="I0" />
<blockpin signalname="Q" name="I1" />
<blockpin signalname="Qnot" name="O" />
</block>
<block symbolname="nand3" name="XLXI_3">
<blockpin signalname="CLK" name="I0" />
<blockpin signalname="J" name="I1" />
<blockpin signalname="Qnot" name="I2" />
<blockpin signalname="XLXN_6" name="O" />
</block>
<block symbolname="nand3" name="XLXI_4">
<blockpin signalname="Q" name="I0" />
<blockpin signalname="K" name="I1" />
<blockpin signalname="CLK" name="I2" />
<blockpin signalname="XLXN_7" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="1312" y="640" name="XLXI_1" orien="R0" />
<instance x="1312" y="992" name="XLXI_2" orien="R0" />
<branch name="Q">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1744" y="544" type="branch" />
<wire x2="976" y1="992" y2="1040" x1="976" />
<wire x2="1680" y1="1040" y2="1040" x1="976" />
<wire x2="1312" y1="816" y2="816" x1="1296" />
<wire x2="1584" y1="816" y2="816" x1="1312" />
<wire x2="1296" y1="816" y2="864" x1="1296" />
<wire x2="1312" y1="864" y2="864" x1="1296" />
<wire x2="1584" y1="544" y2="544" x1="1568" />
<wire x2="1584" y1="544" y2="608" x1="1584" />
<wire x2="1584" y1="608" y2="816" x1="1584" />
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<wire x2="1744" y1="544" y2="544" x1="1680" />
<wire x2="1840" y1="544" y2="544" x1="1744" />
</branch>
<branch name="Qnot">
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<wire x2="1664" y1="416" y2="416" x1="976" />
<wire x2="1664" y1="416" y2="896" x1="1664" />
<wire x2="1744" y1="896" y2="896" x1="1664" />
<wire x2="1824" y1="896" y2="896" x1="1744" />
<wire x2="976" y1="416" y2="448" x1="976" />
<wire x2="1312" y1="576" y2="576" x1="1296" />
<wire x2="1296" y1="576" y2="688" x1="1296" />
<wire x2="1312" y1="688" y2="688" x1="1296" />
<wire x2="1616" y1="688" y2="688" x1="1312" />
<wire x2="1616" y1="688" y2="896" x1="1616" />
<wire x2="1664" y1="896" y2="896" x1="1616" />
<wire x2="1616" y1="896" y2="896" x1="1568" />
</branch>
<instance x="976" y="640" name="XLXI_3" orien="R0" />
<instance x="976" y="1056" name="XLXI_4" orien="R0" />
<branch name="XLXN_6">
<wire x2="1312" y1="512" y2="512" x1="1232" />
</branch>
<branch name="XLXN_7">
<wire x2="1312" y1="928" y2="928" x1="1232" />
</branch>
<branch name="CLK">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="832" y="720" type="branch" />
<wire x2="832" y1="720" y2="720" x1="784" />
<wire x2="896" y1="720" y2="720" x1="832" />
<wire x2="896" y1="720" y2="864" x1="896" />
<wire x2="976" y1="864" y2="864" x1="896" />
<wire x2="976" y1="576" y2="576" x1="896" />
<wire x2="896" y1="576" y2="720" x1="896" />
</branch>
<branch name="J">
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<wire x2="848" y1="512" y2="512" x1="784" />
<wire x2="976" y1="512" y2="512" x1="848" />
</branch>
<branch name="K">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="848" y="928" type="branch" />
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<wire x2="976" y1="928" y2="928" x1="848" />
</branch>
<iomarker fontsize="28" x="1840" y="544" name="Q" orien="R0" />
<iomarker fontsize="28" x="1824" y="896" name="Qnot" orien="R0" />
<iomarker fontsize="28" x="784" y="512" name="J" orien="R180" />
<iomarker fontsize="28" x="784" y="720" name="CLK" orien="R180" />
<iomarker fontsize="28" x="784" y="928" name="K" orien="R180" />
</sheet>
</drawing>

4
AppleIIGateSch/JK_FlipFlop.schlog Normal file
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select figure at 1586 606 8 -branches -sn=1
select figure at 1851 891 8 -branches -sn=1
select figure at 1838 986 8 -branches -sn=1
select figure at 2039 1088 8 -branches -sn=1

24
AppleIIGateSch/JK_FlipFlop.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="JK_FlipFlop">
<symboltype>BLOCK</symboltype>
<timestamp>2018-5-22T0:7:17</timestamp>
<pin polarity="Input" x="0" y="-96" name="CLK" />
<pin polarity="Input" x="0" y="-160" name="J" />
<pin polarity="Input" x="0" y="-32" name="K" />
<pin polarity="Output" x="384" y="-160" name="Q" />
<pin polarity="Output" x="384" y="-32" name="Qnot" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:44;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin CLK" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin J" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin K" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin Q" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin Qnot" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

3
AppleIIGateSch/JK_FlipFlop_JK_FlipFlop_sch_tb_beh.prj Normal file
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verilog work "JK_FlipFlop.vf"
verilog work "JK_FlipFlop_tb.v"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

61
AppleIIGateSch/JK_FlipFlop_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\JK_FlipFlop.sch - Mon May 21 17:10:31 2018
// On positive clock EDGE
// J=0 K=0 outputs Q,Qnot unchanged
// J=1 K=1 outputs Q,Qnot toggled.
// J=1 K=0 outputs Q=1, Qnot=0
// J=0 K=1 outputs Q=0, Qnot=1
`timescale 1ns / 1ps
module JK_FlipFlop_JK_FlipFlop_sch_tb();
// Inputs
reg CLK;
reg J;
reg K;
// Output
wire Q;
wire Qnot;
integer i;
// Bidirs
// Instantiate the UUT
JK_FlipFlop UUT (
.Q(Q),
.Qnot(Qnot),
.CLK(CLK),
.J(J),
.K(K)
);
// Initialize Inputs
// `ifdef auto_init
// initial begin
// CLK = 0;
// J = 0;
// K = 0;
// `endif
initial begin
J=0; K=0; CLK=0;
#2 force UUT.Q_DUMMY = 0; force UUT.Qnot_DUMMY = 1;
#2 CLK=1;
#2 CLK=0;
#2 release UUT.Q_DUMMY;
#2 release UUT.Qnot_DUMMY;
#4;
J = 0;
K = 0;
CLK = 0; #4;
CLK = 1; #4;
for (i=0; i<320; i=i+1) begin
CLK = i & 1;
J = (i >> 1) & 1;
K = (i >> 2) & 1;
$display("CLK=%b J=%b K=%b Q=%b Qnot=%b clock=%d", CLK, J, K, Q, Qnot, $time);
#2;
end
// $finish;
end
endmodule

24
AppleIIGateSch/README.txt Normal file
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I, Frederick Kilner, being of sound mind and body and making a gate level Apple ][ in a FPGA.
Creating a functional gate level Apple II from Apple II schematic.
Using Xilinx 14.7 Schematic Entry. Making small test benches of module.
Design will be loaded in to Nexsys-2 Spartan3E-500 board.
Also manually entering 74series chips(gate level schemtic).
I didn't find a 74series library so have to enter my own chips.
My goal is to have a functional gate level apple II in an FPGA.
I want to be able to connect it to the composite input of a monitor. I'll need a few analog components for that.
Also I will want to have a module which reads the generated composite signal and drives the analog VGA port.
That will probably require a frame buffer unless 59.94Hz refresh rate is okay for some VGA mode.
Voltage level shifters will be needed but I have expansion connections and want to be able to plug in
real Apple II cards including disk drive card and music card and 80 column card.
I want to be able to prototype Apple II hardware changes in FPGA board.
Verilog generated from Xilinx ISE can be used in Xilinx Vivado project to have apple II on Artix-7 chip.
Verilog can be used in other design tool for other chips/boards.. such as Quartus-II or whatever it is now.
FPGA is neat.

108
AppleIIGateSch/chip74LS153_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chipi74LS153.sch - Sun May 27 17:02:08 2018
`timescale 1ns / 1ps
module chipi74LS153_chipi74LS153_sch_tb();
// Inputs
reg Ebn_15;
reg b0_10;
reg b1_11;
reg b2_12;
reg b3_13;
reg Ean_11;
reg a0_6;
reg a1_5;
reg a2_4;
reg a3_3;
reg S0_14;
reg S1_2;
// Output
wire Zb_9;
wire Za_7;
// Simulate test bench vars
integer i, j, errct;
wire [3:0] abus;
wire [3:0] bbus;
assign abus = { a3_3, a2_4, a1_5, a0_6 };
assign bbus = { b3_13, b2_12, b1_11, b0_10 };
reg expectedA, expectedB; // Just for simulation
// Bidirs
// Instantiate the UUT
chipi74LS153 UUT (
.Zb_9(Zb_9),
.Ebn_15(Ebn_15),
.b0_10(b0_10),
.b1_11(b1_11),
.b2_12(b2_12),
.b3_13(b3_13),
.Za_7(Za_7),
.Ean_11(Ean_11),
.a0_6(a0_6),
.a1_5(a1_5),
.a2_4(a2_4),
.a3_3(a3_3),
.S0_14(S0_14),
.S1_2(S1_2)
);
// Initialize Inputs
`ifdef auto_init
initial begin
$display("auto_init is defined");
end
`else
initial begin
$display("not defined auto_init");
end
`endif
initial begin
Ebn_15 = 0;
b0_10 = 0;
b1_11 = 0;
b2_12 = 0;
b3_13 = 0;
Ean_11 = 0;
a0_6 = 0;
a1_5 = 0;
a2_4 = 0;
a3_3 = 0;
S0_14 = 0;
S1_2 = 0;
errct = 0;
#5;
for (i=0; i<256; i=i+1) begin
a0_6 = i[0];
a1_5 = i[1];
a2_4 = i[2];
a3_3 = i[3];
b0_10 = i[4];
b1_11 = i[5];
b2_12 = i[6];
b3_13 = i[7];
#10;
for (j=0; j<16; j=j+1) begin
Ean_11 = j[0];
Ebn_15 = j[1];
S0_14 = j[2];
S1_2 = j[3];
#5;
expectedA = (~Ean_11) & abus[{S1_2,S0_14}];
expectedB = (~Ebn_15) & bbus[{S1_2,S0_14}];
if (expectedA != Za_7) begin
$display("ERR: expectedA=%b Za=%b a=%b S1=%b S0=%b Ean=%b",
expectedA, Za_7, abus, bbus, S1_2, S0_14, Ean_11);
errct = errct + 1;
end
end
end
if ( errct == 0 ) begin
$display("PASSED");
end else begin
$display("FAILED errct=%d", errct);
end
end
endmodule

1
AppleIIGateSch/chip74LS161.jhd Normal file
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MODULE chip74LS161

741
AppleIIGateSch/chip74LS161.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3e" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="XLXN_11" />
<signal name="XLXN_12" />
<signal name="XLXN_13" />
<signal name="CLK" />
<signal name="XLXN_15" />
<signal name="XLXN_17" />
<signal name="XLXN_19" />
<signal name="XLXN_21" />
<signal name="XLXN_26" />
<signal name="XLXN_28" />
<signal name="XLXN_29" />
<signal name="XLXN_35" />
<signal name="XLXN_36" />
<signal name="CLRn" />
<signal name="Q1" />
<signal name="Q2" />
<signal name="Q3" />
<signal name="PEn" />
<signal name="XLXN_44" />
<signal name="XLXN_45" />
<signal name="XLXN_48" />
<signal name="XLXN_50" />
<signal name="XLXN_54" />
<signal name="CEP" />
<signal name="CET" />
<signal name="TC" />
<signal name="P0" />
<signal name="P1" />
<signal name="P2" />
<signal name="P3" />
<signal name="XLXN_64" />
<signal name="XLXN_65" />
<signal name="Q0" />
<signal name="XLXN_71" />
<signal name="XLXN_72" />
<signal name="XLXN_76" />
<signal name="XLXN_77" />
<signal name="XLXN_82" />
<signal name="XLXN_83" />
<signal name="XLXN_84" />
<signal name="XLXN_86" />
<signal name="XLXN_87" />
<port polarity="Input" name="CLK" />
<port polarity="Input" name="CLRn" />
<port polarity="Output" name="Q1" />
<port polarity="Output" name="Q2" />
<port polarity="Output" name="Q3" />
<port polarity="Input" name="PEn" />
<port polarity="Input" name="CEP" />
<port polarity="Input" name="CET" />
<port polarity="Output" name="TC" />
<port polarity="Input" name="P0" />
<port polarity="Input" name="P1" />
<port polarity="Input" name="P2" />
<port polarity="Input" name="P3" />
<port polarity="Output" name="Q0" />
<blockdef name="and2">
<timestamp>2000-1-1T10:10:10</timestamp>
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<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
<blockdef name="or2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
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</blockdef>
<blockdef name="nand2">
<timestamp>2000-1-1T10:10:10</timestamp>
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<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
</blockdef>
<blockdef name="nand3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
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<line x2="64" y1="-64" y2="-192" x1="64" />
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<timestamp>2000-1-1T10:10:10</timestamp>
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<timestamp>2000-1-1T10:10:10</timestamp>
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<timestamp>2000-1-1T10:10:10</timestamp>
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<line x2="64" y1="-320" y2="-320" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-32" y2="-32" x1="192" />
<line x2="192" y1="-64" y2="-32" x1="192" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<line x2="80" y1="-112" y2="-128" x1="64" />
<rect width="256" x="64" y="-384" height="320" />
</blockdef>
<blockdef name="buf">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="128" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="0" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="-64" x1="128" />
<line x2="64" y1="-64" y2="0" x1="64" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="-64" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="0" x1="128" />
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<block symbolname="and2" name="XLXI_5">
<blockpin signalname="XLXN_86" name="I0" />
<blockpin signalname="XLXN_15" name="I1" />
<blockpin signalname="XLXN_64" name="O" />
</block>
<block symbolname="and2" name="XLXI_6">
<blockpin signalname="XLXN_35" name="I0" />
<blockpin signalname="XLXN_86" name="I1" />
<blockpin signalname="XLXN_65" name="O" />
</block>
<block symbolname="and2" name="XLXI_7">
<blockpin signalname="XLXN_11" name="I0" />
<blockpin signalname="XLXN_17" name="I1" />
<blockpin signalname="XLXN_71" name="O" />
</block>
<block symbolname="and2" name="XLXI_8">
<blockpin signalname="XLXN_26" name="I0" />
<blockpin signalname="XLXN_11" name="I1" />
<blockpin signalname="XLXN_72" name="O" />
</block>
<block symbolname="and2" name="XLXI_9">
<blockpin signalname="XLXN_12" name="I0" />
<blockpin signalname="XLXN_19" name="I1" />
<blockpin signalname="XLXN_76" name="O" />
</block>
<block symbolname="and2" name="XLXI_10">
<blockpin signalname="XLXN_28" name="I0" />
<blockpin signalname="XLXN_12" name="I1" />
<blockpin signalname="XLXN_77" name="O" />
</block>
<block symbolname="and2" name="XLXI_11">
<blockpin signalname="XLXN_13" name="I0" />
<blockpin signalname="XLXN_21" name="I1" />
<blockpin signalname="XLXN_82" name="O" />
</block>
<block symbolname="and2" name="XLXI_12">
<blockpin signalname="XLXN_29" name="I0" />
<blockpin signalname="XLXN_13" name="I1" />
<blockpin signalname="XLXN_83" name="O" />
</block>
<block symbolname="or2" name="XLXI_14">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_45" name="I1" />
<blockpin signalname="XLXN_11" name="O" />
</block>
<block symbolname="or2" name="XLXI_15">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_48" name="I1" />
<blockpin signalname="XLXN_12" name="O" />
</block>
<block symbolname="or2" name="XLXI_16">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_50" name="I1" />
<blockpin signalname="XLXN_13" name="O" />
</block>
<block symbolname="or2" name="XLXI_17">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_54" name="I1" />
<blockpin signalname="XLXN_86" name="O" />
</block>
<block symbolname="nand2" name="XLXI_18">
<blockpin signalname="XLXN_35" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_15" name="O" />
</block>
<block symbolname="nand2" name="XLXI_20">
<blockpin signalname="XLXN_26" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_17" name="O" />
</block>
<block symbolname="nand2" name="XLXI_24">
<blockpin signalname="XLXN_28" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_19" name="O" />
</block>
<block symbolname="nand2" name="XLXI_26">
<blockpin signalname="XLXN_29" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_21" name="O" />
</block>
<block symbolname="nand3" name="XLXI_28">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P0" name="I2" />
<blockpin signalname="XLXN_35" name="O" />
</block>
<block symbolname="nand3" name="XLXI_29">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P1" name="I2" />
<blockpin signalname="XLXN_26" name="O" />
</block>
<block symbolname="nand3" name="XLXI_30">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P2" name="I2" />
<blockpin signalname="XLXN_28" name="O" />
</block>
<block symbolname="nand3" name="XLXI_31">
<blockpin signalname="XLXN_44" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="P3" name="I2" />
<blockpin signalname="XLXN_29" name="O" />
</block>
<block symbolname="or2b2" name="XLXI_33">
<blockpin signalname="XLXN_44" name="I0" />
<blockpin signalname="PEn" name="I1" />
<blockpin signalname="XLXN_36" name="O" />
</block>
<block symbolname="and2" name="XLXI_34">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="XLXN_45" name="O" />
</block>
<block symbolname="and3" name="XLXI_35">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="XLXN_48" name="O" />
</block>
<block symbolname="and4" name="XLXI_36">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="Q2" name="I3" />
<blockpin signalname="XLXN_50" name="O" />
</block>
<block symbolname="and5" name="XLXI_37">
<blockpin signalname="CET" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="Q2" name="I3" />
<blockpin signalname="Q3" name="I4" />
<blockpin signalname="TC" name="O" />
</block>
<block symbolname="and2" name="XLXI_38">
<blockpin signalname="CET" name="I0" />
<blockpin signalname="CEP" name="I1" />
<blockpin signalname="XLXN_54" name="O" />
</block>
<block symbolname="fjkc" name="XLXI_39">
<blockpin signalname="XLXN_84" name="C" />
<blockpin signalname="XLXN_87" name="CLR" />
<blockpin signalname="XLXN_64" name="J" />
<blockpin signalname="XLXN_65" name="K" />
<blockpin signalname="Q0" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_40">
<blockpin signalname="XLXN_84" name="C" />
<blockpin signalname="XLXN_87" name="CLR" />
<blockpin signalname="XLXN_71" name="J" />
<blockpin signalname="XLXN_72" name="K" />
<blockpin signalname="Q1" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_41">
<blockpin signalname="XLXN_84" name="C" />
<blockpin signalname="XLXN_87" name="CLR" />
<blockpin signalname="XLXN_76" name="J" />
<blockpin signalname="XLXN_77" name="K" />
<blockpin signalname="Q2" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_42">
<blockpin signalname="XLXN_84" name="C" />
<blockpin signalname="XLXN_87" name="CLR" />
<blockpin signalname="XLXN_82" name="J" />
<blockpin signalname="XLXN_83" name="K" />
<blockpin signalname="Q3" name="Q" />
</block>
<block symbolname="buf" name="XLXI_43">
<blockpin signalname="CLK" name="I" />
<blockpin signalname="XLXN_84" name="O" />
</block>
<block symbolname="buf" name="XLXI_44">
<blockpin signalname="CLRn" name="I" />
<blockpin signalname="XLXN_44" name="O" />
</block>
<block symbolname="inv" name="XLXI_45">
<blockpin signalname="XLXN_44" name="I" />
<blockpin signalname="XLXN_87" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2368" y="1824" name="XLXI_11" orien="R0" />
<branch name="CLK">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="1232" type="branch" />
<wire x2="320" y1="1232" y2="1232" x1="224" />
<wire x2="400" y1="1232" y2="1232" x1="320" />
</branch>
<instance x="1984" y="1120" name="XLXI_14" orien="R0" />
<branch name="XLXN_21">
<wire x2="2368" y1="1696" y2="1696" x1="1920" />
</branch>
<instance x="1664" y="1264" name="XLXI_29" orien="R0" />
<instance x="1664" y="1392" name="XLXI_24" orien="R0" />
<instance x="1664" y="1648" name="XLXI_30" orien="R0" />
<instance x="1664" y="1792" name="XLXI_26" orien="R0" />
<instance x="1664" y="992" name="XLXI_20" orien="R0" />
<branch name="XLXN_26">
<wire x2="1664" y1="928" y2="928" x1="1648" />
<wire x2="1648" y1="928" y2="960" x1="1648" />
<wire x2="1936" y1="960" y2="960" x1="1648" />
<wire x2="1936" y1="960" y2="1136" x1="1936" />
<wire x2="2352" y1="1136" y2="1136" x1="1936" />
<wire x2="1936" y1="1136" y2="1136" x1="1920" />
<wire x2="2368" y1="1056" y2="1056" x1="2352" />
<wire x2="2352" y1="1056" y2="1136" x1="2352" />
</branch>
<branch name="XLXN_28">
<wire x2="1664" y1="1328" y2="1328" x1="1648" />
<wire x2="1648" y1="1328" y2="1360" x1="1648" />
<wire x2="1936" y1="1360" y2="1360" x1="1648" />
<wire x2="1936" y1="1360" y2="1520" x1="1936" />
<wire x2="2160" y1="1520" y2="1520" x1="1936" />
<wire x2="1936" y1="1520" y2="1520" x1="1920" />
<wire x2="2160" y1="1472" y2="1520" x1="2160" />
<wire x2="2384" y1="1472" y2="1472" x1="2160" />
</branch>
<branch name="XLXN_29">
<wire x2="1664" y1="1728" y2="1728" x1="1648" />
<wire x2="1648" y1="1728" y2="1760" x1="1648" />
<wire x2="1936" y1="1760" y2="1760" x1="1648" />
<wire x2="1936" y1="1760" y2="1936" x1="1936" />
<wire x2="1936" y1="1936" y2="1968" x1="1936" />
<wire x2="2144" y1="1936" y2="1936" x1="1936" />
<wire x2="1936" y1="1968" y2="1968" x1="1920" />
<wire x2="2144" y1="1888" y2="1936" x1="2144" />
<wire x2="2368" y1="1888" y2="1888" x1="2144" />
</branch>
<instance x="1664" y="2096" name="XLXI_31" orien="R0" />
<instance x="1984" y="1920" name="XLXI_16" orien="R0" />
<branch name="XLXN_13">
<wire x2="2352" y1="1824" y2="1824" x1="2240" />
<wire x2="2368" y1="1824" y2="1824" x1="2352" />
<wire x2="2368" y1="1760" y2="1760" x1="2352" />
<wire x2="2352" y1="1760" y2="1824" x1="2352" />
</branch>
<instance x="1664" y="544" name="XLXI_18" orien="R0" />
<instance x="1984" y="688" name="XLXI_17" orien="R0" />
<instance x="1664" y="848" name="XLXI_28" orien="R0" />
<branch name="XLXN_35">
<wire x2="1664" y1="480" y2="480" x1="1648" />
<wire x2="1648" y1="480" y2="512" x1="1648" />
<wire x2="1952" y1="512" y2="512" x1="1648" />
<wire x2="1952" y1="512" y2="720" x1="1952" />
<wire x2="2352" y1="720" y2="720" x1="1952" />
<wire x2="1952" y1="720" y2="720" x1="1920" />
<wire x2="2352" y1="576" y2="720" x1="2352" />
<wire x2="2368" y1="576" y2="576" x1="2352" />
</branch>
<branch name="XLXN_36">
<wire x2="1552" y1="416" y2="416" x1="1200" />
<wire x2="1664" y1="416" y2="416" x1="1552" />
<wire x2="1552" y1="416" y2="624" x1="1552" />
<wire x2="1984" y1="624" y2="624" x1="1552" />
<wire x2="1552" y1="624" y2="784" x1="1552" />
<wire x2="1664" y1="784" y2="784" x1="1552" />
<wire x2="1552" y1="784" y2="864" x1="1552" />
<wire x2="1664" y1="864" y2="864" x1="1552" />
<wire x2="1552" y1="864" y2="1056" x1="1552" />
<wire x2="1552" y1="1056" y2="1200" x1="1552" />
<wire x2="1664" y1="1200" y2="1200" x1="1552" />
<wire x2="1552" y1="1200" y2="1264" x1="1552" />
<wire x2="1664" y1="1264" y2="1264" x1="1552" />
<wire x2="1552" y1="1264" y2="1440" x1="1552" />
<wire x2="1552" y1="1440" y2="1584" x1="1552" />
<wire x2="1664" y1="1584" y2="1584" x1="1552" />
<wire x2="1552" y1="1584" y2="1664" x1="1552" />
<wire x2="1664" y1="1664" y2="1664" x1="1552" />
<wire x2="1552" y1="1664" y2="1856" x1="1552" />
<wire x2="1552" y1="1856" y2="1968" x1="1552" />
<wire x2="1664" y1="1968" y2="1968" x1="1552" />
<wire x2="1984" y1="1856" y2="1856" x1="1552" />
<wire x2="1984" y1="1440" y2="1440" x1="1552" />
<wire x2="1984" y1="1056" y2="1056" x1="1552" />
</branch>
<instance x="1984" y="1504" name="XLXI_15" orien="R0" />
<branch name="CLRn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="432" y="2032" type="branch" />
<wire x2="432" y1="2032" y2="2032" x1="368" />
<wire x2="496" y1="2032" y2="2032" x1="432" />
</branch>
<branch name="Q1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="960" type="branch" />
<wire x2="3216" y1="1216" y2="1216" x1="928" />
<wire x2="928" y1="1216" y2="1280" x1="928" />
<wire x2="928" y1="1280" y2="1760" x1="928" />
<wire x2="928" y1="1760" y2="2288" x1="928" />
<wire x2="2768" y1="2288" y2="2288" x1="928" />
<wire x2="1088" y1="1760" y2="1760" x1="928" />
<wire x2="960" y1="1280" y2="1280" x1="928" />
<wire x2="3216" y1="960" y2="960" x1="3104" />
<wire x2="3216" y1="960" y2="1216" x1="3216" />
<wire x2="3328" y1="960" y2="960" x1="3216" />
<wire x2="3392" y1="960" y2="960" x1="3328" />
</branch>
<branch name="Q3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="1792" type="branch" />
<wire x2="2768" y1="2080" y2="2160" x1="2768" />
<wire x2="3216" y1="2080" y2="2080" x1="2768" />
<wire x2="3216" y1="1792" y2="1792" x1="3104" />
<wire x2="3216" y1="1792" y2="2080" x1="3216" />
<wire x2="3328" y1="1792" y2="1792" x1="3216" />
<wire x2="3392" y1="1792" y2="1792" x1="3328" />
</branch>
<instance x="944" y="512" name="XLXI_33" orien="R0" />
<branch name="PEn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="384" type="branch" />
<wire x2="496" y1="384" y2="384" x1="416" />
<wire x2="944" y1="384" y2="384" x1="496" />
</branch>
<instance x="960" y="1088" name="XLXI_34" orien="R0" />
<branch name="XLXN_45">
<wire x2="1984" y1="992" y2="992" x1="1216" />
</branch>
<branch name="XLXN_50">
<wire x2="1984" y1="1792" y2="1792" x1="1344" />
</branch>
<instance x="1088" y="1952" name="XLXI_36" orien="R0" />
<instance x="2768" y="2480" name="XLXI_37" orien="R0" />
<instance x="480" y="2400" name="XLXI_38" orien="R0" />
<branch name="CEP">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2272" type="branch" />
<wire x2="304" y1="2272" y2="2272" x1="224" />
<wire x2="480" y1="2272" y2="2272" x1="304" />
</branch>
<branch name="CET">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2336" type="branch" />
<wire x2="304" y1="2336" y2="2336" x1="224" />
<wire x2="464" y1="2336" y2="2336" x1="304" />
<wire x2="480" y1="2336" y2="2336" x1="464" />
<wire x2="464" y1="2336" y2="2416" x1="464" />
<wire x2="2768" y1="2416" y2="2416" x1="464" />
</branch>
<branch name="TC">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="2288" type="branch" />
<wire x2="3104" y1="2288" y2="2288" x1="3024" />
<wire x2="3184" y1="2288" y2="2288" x1="3104" />
</branch>
<branch name="P0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="656" type="branch" />
<wire x2="496" y1="656" y2="656" x1="432" />
<wire x2="1664" y1="656" y2="656" x1="496" />
</branch>
<branch name="P1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1072" type="branch" />
<wire x2="512" y1="1072" y2="1072" x1="448" />
<wire x2="1664" y1="1072" y2="1072" x1="512" />
</branch>
<instance x="960" y="1472" name="XLXI_35" orien="R0" />
<branch name="XLXN_54">
<wire x2="848" y1="2304" y2="2304" x1="736" />
<wire x2="1984" y1="560" y2="560" x1="848" />
<wire x2="848" y1="560" y2="1024" x1="848" />
<wire x2="960" y1="1024" y2="1024" x1="848" />
<wire x2="848" y1="1024" y2="1408" x1="848" />
<wire x2="960" y1="1408" y2="1408" x1="848" />
<wire x2="848" y1="1408" y2="1888" x1="848" />
<wire x2="1088" y1="1888" y2="1888" x1="848" />
<wire x2="848" y1="1888" y2="2304" x1="848" />
</branch>
<branch name="XLXN_48">
<wire x2="1584" y1="1344" y2="1344" x1="1216" />
<wire x2="1584" y1="1344" y2="1376" x1="1584" />
<wire x2="1984" y1="1376" y2="1376" x1="1584" />
</branch>
<branch name="P2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1456" type="branch" />
<wire x2="512" y1="1456" y2="1456" x1="432" />
<wire x2="1664" y1="1456" y2="1456" x1="512" />
</branch>
<branch name="P3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1920" type="branch" />
<wire x2="512" y1="1920" y2="1920" x1="416" />
<wire x2="1664" y1="1920" y2="1920" x1="512" />
<wire x2="1664" y1="1904" y2="1920" x1="1664" />
</branch>
<text style="fontsize:24;fontname:Arial" x="2464" y="152">Q0,Q1,Q2,Q3 is Qa,Qb,Qc,Qd from TTL book</text>
<text style="fontsize:24;fontname:Arial" x="3008" y="2168">TC is RCO from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="188" y="2196">CET CEP same as ENT ENP from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="180" y="584">P0 is DATA_A, P1 is DATA_B ... from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="340" y="308">PEn is LOADn from TTL Book</text>
<iomarker fontsize="28" x="432" y="656" name="P0" orien="R180" />
<iomarker fontsize="28" x="448" y="1072" name="P1" orien="R180" />
<iomarker fontsize="28" x="224" y="1232" name="CLK" orien="R180" />
<iomarker fontsize="28" x="432" y="1456" name="P2" orien="R180" />
<iomarker fontsize="28" x="416" y="1920" name="P3" orien="R180" />
<iomarker fontsize="28" x="224" y="2272" name="CEP" orien="R180" />
<iomarker fontsize="28" x="224" y="2336" name="CET" orien="R180" />
<iomarker fontsize="28" x="3392" y="960" name="Q1" orien="R0" />
<iomarker fontsize="28" x="3184" y="2288" name="TC" orien="R0" />
<iomarker fontsize="28" x="416" y="384" name="PEn" orien="R180" />
<instance x="2720" y="736" name="XLXI_39" orien="R0" />
<instance x="2368" y="512" name="XLXI_5" orien="R0" />
<branch name="XLXN_15">
<wire x2="1936" y1="448" y2="448" x1="1920" />
<wire x2="2368" y1="384" y2="384" x1="1936" />
<wire x2="1936" y1="384" y2="448" x1="1936" />
</branch>
<branch name="XLXN_64">
<wire x2="2720" y1="416" y2="416" x1="2624" />
</branch>
<instance x="2368" y="640" name="XLXI_6" orien="R0" />
<branch name="XLXN_65">
<wire x2="2672" y1="544" y2="544" x1="2624" />
<wire x2="2672" y1="480" y2="544" x1="2672" />
<wire x2="2720" y1="480" y2="480" x1="2672" />
</branch>
<branch name="Q0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3312" y="480" type="branch" />
<wire x2="880" y1="816" y2="960" x1="880" />
<wire x2="960" y1="960" y2="960" x1="880" />
<wire x2="880" y1="960" y2="1344" x1="880" />
<wire x2="960" y1="1344" y2="1344" x1="880" />
<wire x2="880" y1="1344" y2="1824" x1="880" />
<wire x2="880" y1="1824" y2="2352" x1="880" />
<wire x2="2768" y1="2352" y2="2352" x1="880" />
<wire x2="1088" y1="1824" y2="1824" x1="880" />
<wire x2="3184" y1="816" y2="816" x1="880" />
<wire x2="3184" y1="480" y2="480" x1="3104" />
<wire x2="3184" y1="480" y2="816" x1="3184" />
<wire x2="3312" y1="480" y2="480" x1="3184" />
<wire x2="3376" y1="480" y2="480" x1="3312" />
</branch>
<iomarker fontsize="28" x="3376" y="480" name="Q0" orien="R0" />
<instance x="2720" y="1216" name="XLXI_40" orien="R0" />
<instance x="2368" y="992" name="XLXI_7" orien="R0" />
<branch name="XLXN_17">
<wire x2="1936" y1="896" y2="896" x1="1920" />
<wire x2="2368" y1="864" y2="864" x1="1936" />
<wire x2="1936" y1="864" y2="896" x1="1936" />
</branch>
<branch name="XLXN_11">
<wire x2="2352" y1="1024" y2="1024" x1="2240" />
<wire x2="2368" y1="928" y2="928" x1="2352" />
<wire x2="2352" y1="928" y2="992" x1="2352" />
<wire x2="2368" y1="992" y2="992" x1="2352" />
<wire x2="2352" y1="992" y2="1024" x1="2352" />
</branch>
<instance x="2368" y="1120" name="XLXI_8" orien="R0" />
<branch name="XLXN_71">
<wire x2="2720" y1="896" y2="896" x1="2624" />
</branch>
<branch name="XLXN_72">
<wire x2="2672" y1="1024" y2="1024" x1="2624" />
<wire x2="2672" y1="960" y2="1024" x1="2672" />
<wire x2="2720" y1="960" y2="960" x1="2672" />
</branch>
<instance x="2720" y="1632" name="XLXI_41" orien="R0" />
<instance x="2384" y="1408" name="XLXI_9" orien="R0" />
<branch name="XLXN_19">
<wire x2="1936" y1="1296" y2="1296" x1="1920" />
<wire x2="2384" y1="1280" y2="1280" x1="1936" />
<wire x2="1936" y1="1280" y2="1296" x1="1936" />
</branch>
<branch name="XLXN_12">
<wire x2="2368" y1="1408" y2="1408" x1="2240" />
<wire x2="2384" y1="1408" y2="1408" x1="2368" />
<wire x2="2384" y1="1344" y2="1344" x1="2368" />
<wire x2="2368" y1="1344" y2="1408" x1="2368" />
</branch>
<instance x="2384" y="1536" name="XLXI_10" orien="R0" />
<branch name="XLXN_76">
<wire x2="2720" y1="1312" y2="1312" x1="2640" />
</branch>
<branch name="XLXN_77">
<wire x2="2672" y1="1440" y2="1440" x1="2640" />
<wire x2="2672" y1="1376" y2="1440" x1="2672" />
<wire x2="2720" y1="1376" y2="1376" x1="2672" />
</branch>
<iomarker fontsize="28" x="3392" y="1376" name="Q2" orien="R0" />
<branch name="Q2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3344" y="1376" type="branch" />
<wire x2="1024" y1="1632" y2="1696" x1="1024" />
<wire x2="1088" y1="1696" y2="1696" x1="1024" />
<wire x2="1024" y1="1696" y2="2224" x1="1024" />
<wire x2="2768" y1="2224" y2="2224" x1="1024" />
<wire x2="3232" y1="1632" y2="1632" x1="1024" />
<wire x2="3232" y1="1376" y2="1376" x1="3104" />
<wire x2="3232" y1="1376" y2="1632" x1="3232" />
<wire x2="3344" y1="1376" y2="1376" x1="3232" />
<wire x2="3392" y1="1376" y2="1376" x1="3344" />
</branch>
<instance x="2720" y="2048" name="XLXI_42" orien="R0" />
<instance x="2368" y="1952" name="XLXI_12" orien="R0" />
<branch name="XLXN_82">
<wire x2="2720" y1="1728" y2="1728" x1="2624" />
</branch>
<branch name="XLXN_83">
<wire x2="2672" y1="1856" y2="1856" x1="2624" />
<wire x2="2672" y1="1792" y2="1856" x1="2672" />
<wire x2="2720" y1="1792" y2="1792" x1="2672" />
</branch>
<iomarker fontsize="28" x="3392" y="1792" name="Q3" orien="R0" />
<branch name="XLXN_86">
<wire x2="2304" y1="592" y2="592" x1="2240" />
<wire x2="2368" y1="448" y2="448" x1="2304" />
<wire x2="2304" y1="448" y2="512" x1="2304" />
<wire x2="2304" y1="512" y2="592" x1="2304" />
<wire x2="2368" y1="512" y2="512" x1="2304" />
</branch>
<iomarker fontsize="28" x="368" y="2032" name="CLRn" orien="R180" />
<instance x="400" y="1264" name="XLXI_43" orien="R0" />
<branch name="XLXN_84">
<wire x2="2304" y1="1232" y2="1232" x1="624" />
<wire x2="2304" y1="1232" y2="1520" x1="2304" />
<wire x2="2720" y1="1520" y2="1520" x1="2304" />
<wire x2="2304" y1="1520" y2="1936" x1="2304" />
<wire x2="2544" y1="1936" y2="1936" x1="2304" />
<wire x2="2416" y1="752" y2="752" x1="2304" />
<wire x2="2304" y1="752" y2="1104" x1="2304" />
<wire x2="2512" y1="1104" y2="1104" x1="2304" />
<wire x2="2304" y1="1104" y2="1232" x1="2304" />
<wire x2="2416" y1="640" y2="752" x1="2416" />
<wire x2="2720" y1="640" y2="640" x1="2416" />
<wire x2="2720" y1="1088" y2="1088" x1="2512" />
<wire x2="2512" y1="1088" y2="1104" x1="2512" />
<wire x2="2720" y1="1920" y2="1920" x1="2544" />
<wire x2="2544" y1="1920" y2="1936" x1="2544" />
<wire x2="2720" y1="608" y2="640" x1="2720" />
<wire x2="2720" y1="1504" y2="1520" x1="2720" />
</branch>
<instance x="496" y="2064" name="XLXI_44" orien="R0" />
<branch name="XLXN_87">
<wire x2="2304" y1="2144" y2="2144" x1="2224" />
<wire x2="2304" y1="2016" y2="2144" x1="2304" />
<wire x2="2704" y1="2016" y2="2016" x1="2304" />
<wire x2="2720" y1="2016" y2="2016" x1="2704" />
<wire x2="2720" y1="704" y2="704" x1="2704" />
<wire x2="2704" y1="704" y2="1184" x1="2704" />
<wire x2="2720" y1="1184" y2="1184" x1="2704" />
<wire x2="2704" y1="1184" y2="1600" x1="2704" />
<wire x2="2720" y1="1600" y2="1600" x1="2704" />
<wire x2="2704" y1="1600" y2="2016" x1="2704" />
</branch>
<branch name="XLXN_44">
<wire x2="784" y1="2032" y2="2032" x1="720" />
<wire x2="1456" y1="2032" y2="2032" x1="784" />
<wire x2="1616" y1="2032" y2="2032" x1="1456" />
<wire x2="1664" y1="2032" y2="2032" x1="1616" />
<wire x2="1616" y1="2032" y2="2144" x1="1616" />
<wire x2="1936" y1="2144" y2="2144" x1="1616" />
<wire x2="2000" y1="2144" y2="2144" x1="1936" />
<wire x2="944" y1="448" y2="448" x1="784" />
<wire x2="784" y1="448" y2="2032" x1="784" />
<wire x2="1664" y1="720" y2="720" x1="1456" />
<wire x2="1456" y1="720" y2="1136" x1="1456" />
<wire x2="1664" y1="1136" y2="1136" x1="1456" />
<wire x2="1456" y1="1136" y2="1520" x1="1456" />
<wire x2="1664" y1="1520" y2="1520" x1="1456" />
<wire x2="1456" y1="1520" y2="2032" x1="1456" />
</branch>
<instance x="2000" y="2176" name="XLXI_45" orien="R0" />
</sheet>
</drawing>

736
AppleIIGateSch/chip74LS161.schbak Normal file
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@ -0,0 +1,736 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3e" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="XLXN_1" />
<signal name="XLXN_2" />
<signal name="XLXN_3" />
<signal name="XLXN_4" />
<signal name="XLXN_5" />
<signal name="XLXN_6" />
<signal name="XLXN_7" />
<signal name="XLXN_8" />
<signal name="XLXN_9" />
<signal name="XLXN_10" />
<signal name="XLXN_11" />
<signal name="XLXN_12" />
<signal name="XLXN_13" />
<signal name="CLK" />
<signal name="XLXN_15" />
<signal name="XLXN_16" />
<signal name="XLXN_17" />
<signal name="XLXN_18" />
<signal name="XLXN_19" />
<signal name="XLXN_20" />
<signal name="XLXN_21" />
<signal name="XLXN_22" />
<signal name="XLXN_24" />
<signal name="XLXN_26" />
<signal name="XLXN_28" />
<signal name="XLXN_29" />
<signal name="XLXN_33" />
<signal name="XLXN_34" />
<signal name="XLXN_35" />
<signal name="XLXN_36" />
<signal name="XLXN_37" />
<signal name="CLRn" />
<signal name="Q0" />
<signal name="Q1" />
<signal name="Q2" />
<signal name="Q3" />
<signal name="LOADn" />
<signal name="XLXN_44" />
<signal name="XLXN_45" />
<signal name="XLXN_47" />
<signal name="XLXN_48" />
<signal name="XLXN_49" />
<signal name="XLXN_50" />
<signal name="XLXN_51" />
<signal name="XLXN_52" />
<signal name="XLXN_53" />
<signal name="XLXN_54" />
<signal name="XLXN_55" />
<signal name="XLXN_56" />
<signal name="CEP" />
<signal name="CET" />
<signal name="XLXN_59" />
<signal name="TC" />
<signal name="P0" />
<signal name="P1" />
<signal name="P2" />
<signal name="P3" />
<port polarity="Input" name="CLK" />
<port polarity="Input" name="CLRn" />
<port polarity="Output" name="Q0" />
<port polarity="Output" name="Q1" />
<port polarity="Output" name="Q2" />
<port polarity="Output" name="Q3" />
<port polarity="Input" name="LOADn" />
<port polarity="Input" name="CEP" />
<port polarity="Input" name="CET" />
<port polarity="Output" name="TC" />
<port polarity="Input" name="P0" />
<port polarity="Input" name="P1" />
<port polarity="Input" name="P2" />
<port polarity="Input" name="P3" />
<blockdef name="JK_FlipFlop">
<timestamp>2018-5-22T0:7:17</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<blockdef name="and2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="192" y1="-96" y2="-96" x1="256" />
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
<line x2="64" y1="-48" y2="-48" x1="144" />
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="-64" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="0" x1="128" />
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<blockdef name="or2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="192" y1="-96" y2="-96" x1="256" />
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
<line x2="48" y1="-144" y2="-144" x1="112" />
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
<line x2="48" y1="-48" y2="-48" x1="112" />
</blockdef>
<blockdef name="nand2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="216" y1="-96" y2="-96" x1="256" />
<circle r="12" cx="204" cy="-96" />
<line x2="64" y1="-48" y2="-144" x1="64" />
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-48" x1="144" />
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
</blockdef>
<blockdef name="nand3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="216" y1="-128" y2="-128" x1="256" />
<circle r="12" cx="204" cy="-128" />
<line x2="144" y1="-176" y2="-176" x1="64" />
<line x2="64" y1="-80" y2="-80" x1="144" />
<arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
<line x2="64" y1="-64" y2="-192" x1="64" />
</blockdef>
<blockdef name="or2b2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="32" y1="-64" y2="-64" x1="0" />
<circle r="12" cx="44" cy="-64" />
<line x2="32" y1="-128" y2="-128" x1="0" />
<circle r="12" cx="44" cy="-128" />
<line x2="192" y1="-96" y2="-96" x1="256" />
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
<line x2="48" y1="-48" y2="-48" x1="112" />
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
<line x2="48" y1="-144" y2="-144" x1="112" />
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
</blockdef>
<blockdef name="and3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="192" y1="-128" y2="-128" x1="256" />
<line x2="144" y1="-176" y2="-176" x1="64" />
<line x2="64" y1="-80" y2="-80" x1="144" />
<arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
<line x2="64" y1="-64" y2="-192" x1="64" />
</blockdef>
<blockdef name="and4">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-112" y2="-112" x1="144" />
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
<line x2="144" y1="-208" y2="-208" x1="64" />
<line x2="64" y1="-64" y2="-256" x1="64" />
<line x2="192" y1="-160" y2="-160" x1="256" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-64" y2="-64" x1="0" />
</blockdef>
<blockdef name="and5">
<timestamp>2000-1-1T10:10:10</timestamp>
<arc ex="144" ey="-240" sx="144" sy="-144" r="48" cx="144" cy="-192" />
<line x2="64" y1="-144" y2="-144" x1="144" />
<line x2="144" y1="-240" y2="-240" x1="64" />
<line x2="64" y1="-64" y2="-320" x1="64" />
<line x2="192" y1="-192" y2="-192" x1="256" />
<line x2="64" y1="-320" y2="-320" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-64" y2="-64" x1="0" />
</blockdef>
<block symbolname="JK_FlipFlop" name="XLXI_1">
<blockpin signalname="XLXN_9" name="CLK" />
<blockpin signalname="XLXN_1" name="J" />
<blockpin signalname="XLXN_2" name="K" />
<blockpin signalname="Q0" name="Q" />
<blockpin name="Qnot" />
</block>
<block symbolname="JK_FlipFlop" name="XLXI_2">
<blockpin signalname="XLXN_9" name="CLK" />
<blockpin signalname="XLXN_3" name="J" />
<blockpin signalname="XLXN_4" name="K" />
<blockpin signalname="Q1" name="Q" />
<blockpin name="Qnot" />
</block>
<block symbolname="JK_FlipFlop" name="XLXI_3">
<blockpin signalname="XLXN_9" name="CLK" />
<blockpin signalname="XLXN_5" name="J" />
<blockpin signalname="XLXN_6" name="K" />
<blockpin signalname="Q2" name="Q" />
<blockpin name="Qnot" />
</block>
<block symbolname="JK_FlipFlop" name="XLXI_4">
<blockpin signalname="XLXN_9" name="CLK" />
<blockpin signalname="XLXN_7" name="J" />
<blockpin signalname="XLXN_8" name="K" />
<blockpin signalname="Q3" name="Q" />
<blockpin signalname="XLXN_55" name="Qnot" />
</block>
<block symbolname="and2" name="XLXI_5">
<blockpin signalname="XLXN_10" name="I0" />
<blockpin signalname="XLXN_15" name="I1" />
<blockpin signalname="XLXN_1" name="O" />
</block>
<block symbolname="and2" name="XLXI_6">
<blockpin signalname="XLXN_35" name="I0" />
<blockpin signalname="XLXN_10" name="I1" />
<blockpin signalname="XLXN_2" name="O" />
</block>
<block symbolname="and2" name="XLXI_7">
<blockpin signalname="XLXN_11" name="I0" />
<blockpin signalname="XLXN_17" name="I1" />
<blockpin signalname="XLXN_3" name="O" />
</block>
<block symbolname="and2" name="XLXI_8">
<blockpin signalname="XLXN_26" name="I0" />
<blockpin signalname="XLXN_11" name="I1" />
<blockpin signalname="XLXN_4" name="O" />
</block>
<block symbolname="and2" name="XLXI_9">
<blockpin signalname="XLXN_12" name="I0" />
<blockpin signalname="XLXN_19" name="I1" />
<blockpin signalname="XLXN_5" name="O" />
</block>
<block symbolname="and2" name="XLXI_10">
<blockpin signalname="XLXN_28" name="I0" />
<blockpin signalname="XLXN_12" name="I1" />
<blockpin signalname="XLXN_6" name="O" />
</block>
<block symbolname="and2" name="XLXI_11">
<blockpin signalname="XLXN_13" name="I0" />
<blockpin signalname="XLXN_21" name="I1" />
<blockpin signalname="XLXN_7" name="O" />
</block>
<block symbolname="and2" name="XLXI_12">
<blockpin signalname="XLXN_29" name="I0" />
<blockpin signalname="XLXN_13" name="I1" />
<blockpin signalname="XLXN_8" name="O" />
</block>
<block symbolname="inv" name="XLXI_13">
<blockpin signalname="CLK" name="I" />
<blockpin signalname="XLXN_9" name="O" />
</block>
<block symbolname="or2" name="XLXI_14">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_45" name="I1" />
<blockpin signalname="XLXN_11" name="O" />
</block>
<block symbolname="or2" name="XLXI_15">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_48" name="I1" />
<blockpin signalname="XLXN_12" name="O" />
</block>
<block symbolname="or2" name="XLXI_16">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_50" name="I1" />
<blockpin signalname="XLXN_13" name="O" />
</block>
<block symbolname="or2" name="XLXI_17">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_54" name="I1" />
<blockpin signalname="XLXN_10" name="O" />
</block>
<block symbolname="nand2" name="XLXI_18">
<blockpin signalname="XLXN_35" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_15" name="O" />
</block>
<block symbolname="nand2" name="XLXI_20">
<blockpin signalname="XLXN_26" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_17" name="O" />
</block>
<block symbolname="nand2" name="XLXI_24">
<blockpin signalname="XLXN_28" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_19" name="O" />
</block>
<block symbolname="nand2" name="XLXI_26">
<blockpin signalname="XLXN_29" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="XLXN_21" name="O" />
</block>
<block symbolname="nand3" name="XLXI_28">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P0" name="I2" />
<blockpin signalname="XLXN_35" name="O" />
</block>
<block symbolname="nand3" name="XLXI_29">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P1" name="I2" />
<blockpin signalname="XLXN_26" name="O" />
</block>
<block symbolname="nand3" name="XLXI_30">
<blockpin signalname="XLXN_36" name="I0" />
<blockpin signalname="XLXN_44" name="I1" />
<blockpin signalname="P2" name="I2" />
<blockpin signalname="XLXN_28" name="O" />
</block>
<block symbolname="nand3" name="XLXI_31">
<blockpin signalname="XLXN_44" name="I0" />
<blockpin signalname="XLXN_36" name="I1" />
<blockpin signalname="P3" name="I2" />
<blockpin signalname="XLXN_29" name="O" />
</block>
<block symbolname="inv" name="XLXI_32">
<blockpin signalname="CLRn" name="I" />
<blockpin signalname="XLXN_44" name="O" />
</block>
<block symbolname="or2b2" name="XLXI_33">
<blockpin signalname="XLXN_44" name="I0" />
<blockpin signalname="LOADn" name="I1" />
<blockpin signalname="XLXN_36" name="O" />
</block>
<block symbolname="and2" name="XLXI_34">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="XLXN_45" name="O" />
</block>
<block symbolname="and3" name="XLXI_35">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="XLXN_48" name="O" />
</block>
<block symbolname="and4" name="XLXI_36">
<blockpin signalname="XLXN_54" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="Q2" name="I3" />
<blockpin signalname="XLXN_50" name="O" />
</block>
<block symbolname="and5" name="XLXI_37">
<blockpin signalname="CET" name="I0" />
<blockpin signalname="Q0" name="I1" />
<blockpin signalname="Q1" name="I2" />
<blockpin signalname="Q2" name="I3" />
<blockpin signalname="XLXN_55" name="I4" />
<blockpin signalname="TC" name="O" />
</block>
<block symbolname="and2" name="XLXI_38">
<blockpin signalname="CET" name="I0" />
<blockpin signalname="CEP" name="I1" />
<blockpin signalname="XLXN_54" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2688" y="704" name="XLXI_1" orien="R0">
</instance>
<instance x="2688" y="1120" name="XLXI_2" orien="R0">
</instance>
<instance x="2688" y="1504" name="XLXI_3" orien="R0">
</instance>
<instance x="2688" y="1904" name="XLXI_4" orien="R0">
</instance>
<branch name="XLXN_1">
<wire x2="2672" y1="528" y2="528" x1="2624" />
<wire x2="2672" y1="528" y2="544" x1="2672" />
<wire x2="2688" y1="544" y2="544" x1="2672" />
</branch>
<branch name="XLXN_2">
<wire x2="2672" y1="688" y2="688" x1="2624" />
<wire x2="2688" y1="672" y2="672" x1="2672" />
<wire x2="2672" y1="672" y2="688" x1="2672" />
</branch>
<branch name="XLXN_3">
<wire x2="2672" y1="944" y2="944" x1="2624" />
<wire x2="2672" y1="944" y2="960" x1="2672" />
<wire x2="2688" y1="960" y2="960" x1="2672" />
</branch>
<branch name="XLXN_4">
<wire x2="2672" y1="1104" y2="1104" x1="2624" />
<wire x2="2688" y1="1088" y2="1088" x1="2672" />
<wire x2="2672" y1="1088" y2="1104" x1="2672" />
</branch>
<branch name="XLXN_5">
<wire x2="2672" y1="1328" y2="1328" x1="2624" />
<wire x2="2672" y1="1328" y2="1344" x1="2672" />
<wire x2="2688" y1="1344" y2="1344" x1="2672" />
</branch>
<branch name="XLXN_6">
<wire x2="2672" y1="1488" y2="1488" x1="2624" />
<wire x2="2688" y1="1472" y2="1472" x1="2672" />
<wire x2="2672" y1="1472" y2="1488" x1="2672" />
</branch>
<branch name="XLXN_7">
<wire x2="2672" y1="1728" y2="1728" x1="2624" />
<wire x2="2672" y1="1728" y2="1744" x1="2672" />
<wire x2="2688" y1="1744" y2="1744" x1="2672" />
</branch>
<branch name="XLXN_8">
<wire x2="2672" y1="1888" y2="1888" x1="2624" />
<wire x2="2688" y1="1872" y2="1872" x1="2672" />
<wire x2="2672" y1="1872" y2="1888" x1="2672" />
</branch>
<branch name="XLXN_9">
<wire x2="2304" y1="1232" y2="1232" x1="656" />
<wire x2="2304" y1="1232" y2="1408" x1="2304" />
<wire x2="2304" y1="1408" y2="1808" x1="2304" />
<wire x2="2688" y1="1808" y2="1808" x1="2304" />
<wire x2="2688" y1="1408" y2="1408" x1="2304" />
<wire x2="2688" y1="608" y2="608" x1="2304" />
<wire x2="2304" y1="608" y2="1024" x1="2304" />
<wire x2="2688" y1="1024" y2="1024" x1="2304" />
<wire x2="2304" y1="1024" y2="1232" x1="2304" />
</branch>
<instance x="2368" y="624" name="XLXI_5" orien="R0" />
<instance x="2368" y="784" name="XLXI_6" orien="R0" />
<instance x="2368" y="1040" name="XLXI_7" orien="R0" />
<instance x="2368" y="1200" name="XLXI_8" orien="R0" />
<instance x="2368" y="1424" name="XLXI_9" orien="R0" />
<instance x="2368" y="1584" name="XLXI_10" orien="R0" />
<instance x="2368" y="1824" name="XLXI_11" orien="R0" />
<instance x="2368" y="1984" name="XLXI_12" orien="R0" />
<branch name="XLXN_11">
<wire x2="2272" y1="1024" y2="1024" x1="2240" />
<wire x2="2272" y1="1024" y2="1072" x1="2272" />
<wire x2="2368" y1="1072" y2="1072" x1="2272" />
<wire x2="2368" y1="976" y2="976" x1="2272" />
<wire x2="2272" y1="976" y2="1024" x1="2272" />
</branch>
<branch name="CLK">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="1232" type="branch" />
<wire x2="320" y1="1232" y2="1232" x1="224" />
<wire x2="432" y1="1232" y2="1232" x1="320" />
</branch>
<instance x="1984" y="1120" name="XLXI_14" orien="R0" />
<branch name="XLXN_15">
<wire x2="2352" y1="448" y2="448" x1="1920" />
<wire x2="2352" y1="448" y2="496" x1="2352" />
<wire x2="2368" y1="496" y2="496" x1="2352" />
</branch>
<branch name="XLXN_17">
<wire x2="2352" y1="896" y2="896" x1="1920" />
<wire x2="2352" y1="896" y2="912" x1="2352" />
<wire x2="2368" y1="912" y2="912" x1="2352" />
</branch>
<branch name="XLXN_19">
<wire x2="2368" y1="1296" y2="1296" x1="1920" />
</branch>
<branch name="XLXN_21">
<wire x2="2368" y1="1696" y2="1696" x1="1920" />
</branch>
<instance x="1664" y="1264" name="XLXI_29" orien="R0" />
<instance x="1664" y="1392" name="XLXI_24" orien="R0" />
<instance x="1664" y="1648" name="XLXI_30" orien="R0" />
<instance x="1664" y="1792" name="XLXI_26" orien="R0" />
<instance x="1664" y="992" name="XLXI_20" orien="R0" />
<branch name="XLXN_26">
<wire x2="1664" y1="928" y2="928" x1="1648" />
<wire x2="1648" y1="928" y2="960" x1="1648" />
<wire x2="1936" y1="960" y2="960" x1="1648" />
<wire x2="1936" y1="960" y2="1136" x1="1936" />
<wire x2="2368" y1="1136" y2="1136" x1="1936" />
<wire x2="1936" y1="1136" y2="1136" x1="1920" />
</branch>
<branch name="XLXN_12">
<wire x2="2272" y1="1408" y2="1408" x1="2240" />
<wire x2="2272" y1="1408" y2="1456" x1="2272" />
<wire x2="2368" y1="1456" y2="1456" x1="2272" />
<wire x2="2368" y1="1360" y2="1360" x1="2272" />
<wire x2="2272" y1="1360" y2="1408" x1="2272" />
</branch>
<branch name="XLXN_28">
<wire x2="1664" y1="1328" y2="1328" x1="1648" />
<wire x2="1648" y1="1328" y2="1360" x1="1648" />
<wire x2="1936" y1="1360" y2="1360" x1="1648" />
<wire x2="1936" y1="1360" y2="1520" x1="1936" />
<wire x2="2368" y1="1520" y2="1520" x1="1936" />
<wire x2="1936" y1="1520" y2="1520" x1="1920" />
</branch>
<branch name="XLXN_29">
<wire x2="1664" y1="1728" y2="1728" x1="1648" />
<wire x2="1648" y1="1728" y2="1760" x1="1648" />
<wire x2="1936" y1="1760" y2="1760" x1="1648" />
<wire x2="1936" y1="1760" y2="1936" x1="1936" />
<wire x2="2352" y1="1936" y2="1936" x1="1936" />
<wire x2="1936" y1="1936" y2="1968" x1="1936" />
<wire x2="1936" y1="1968" y2="1968" x1="1920" />
<wire x2="2368" y1="1920" y2="1920" x1="2352" />
<wire x2="2352" y1="1920" y2="1936" x1="2352" />
</branch>
<instance x="1664" y="2096" name="XLXI_31" orien="R0" />
<instance x="1984" y="1920" name="XLXI_16" orien="R0" />
<branch name="XLXN_13">
<wire x2="2256" y1="1824" y2="1824" x1="2240" />
<wire x2="2256" y1="1808" y2="1824" x1="2256" />
<wire x2="2272" y1="1808" y2="1808" x1="2256" />
<wire x2="2272" y1="1808" y2="1856" x1="2272" />
<wire x2="2368" y1="1856" y2="1856" x1="2272" />
<wire x2="2368" y1="1760" y2="1760" x1="2272" />
<wire x2="2272" y1="1760" y2="1808" x1="2272" />
</branch>
<instance x="1664" y="544" name="XLXI_18" orien="R0" />
<instance x="1984" y="688" name="XLXI_17" orien="R0" />
<branch name="XLXN_10">
<wire x2="2256" y1="592" y2="592" x1="2240" />
<wire x2="2256" y1="592" y2="608" x1="2256" />
<wire x2="2272" y1="608" y2="608" x1="2256" />
<wire x2="2272" y1="608" y2="656" x1="2272" />
<wire x2="2368" y1="656" y2="656" x1="2272" />
<wire x2="2368" y1="560" y2="560" x1="2272" />
<wire x2="2272" y1="560" y2="608" x1="2272" />
</branch>
<instance x="1664" y="848" name="XLXI_28" orien="R0" />
<branch name="XLXN_35">
<wire x2="1664" y1="480" y2="480" x1="1648" />
<wire x2="1648" y1="480" y2="512" x1="1648" />
<wire x2="1952" y1="512" y2="512" x1="1648" />
<wire x2="1952" y1="512" y2="720" x1="1952" />
<wire x2="2368" y1="720" y2="720" x1="1952" />
<wire x2="1952" y1="720" y2="720" x1="1920" />
</branch>
<branch name="XLXN_36">
<wire x2="1552" y1="416" y2="416" x1="1200" />
<wire x2="1664" y1="416" y2="416" x1="1552" />
<wire x2="1552" y1="416" y2="624" x1="1552" />
<wire x2="1984" y1="624" y2="624" x1="1552" />
<wire x2="1552" y1="624" y2="784" x1="1552" />
<wire x2="1664" y1="784" y2="784" x1="1552" />
<wire x2="1552" y1="784" y2="864" x1="1552" />
<wire x2="1664" y1="864" y2="864" x1="1552" />
<wire x2="1552" y1="864" y2="1056" x1="1552" />
<wire x2="1552" y1="1056" y2="1200" x1="1552" />
<wire x2="1664" y1="1200" y2="1200" x1="1552" />
<wire x2="1552" y1="1200" y2="1264" x1="1552" />
<wire x2="1664" y1="1264" y2="1264" x1="1552" />
<wire x2="1552" y1="1264" y2="1440" x1="1552" />
<wire x2="1552" y1="1440" y2="1584" x1="1552" />
<wire x2="1664" y1="1584" y2="1584" x1="1552" />
<wire x2="1552" y1="1584" y2="1664" x1="1552" />
<wire x2="1664" y1="1664" y2="1664" x1="1552" />
<wire x2="1552" y1="1664" y2="1856" x1="1552" />
<wire x2="1552" y1="1856" y2="1968" x1="1552" />
<wire x2="1552" y1="1968" y2="1984" x1="1552" />
<wire x2="1664" y1="1968" y2="1968" x1="1552" />
<wire x2="1984" y1="1856" y2="1856" x1="1552" />
<wire x2="1984" y1="1440" y2="1440" x1="1552" />
<wire x2="1984" y1="1056" y2="1056" x1="1552" />
</branch>
<instance x="1984" y="1504" name="XLXI_15" orien="R0" />
<instance x="512" y="2096" name="XLXI_32" orien="R0" />
<branch name="CLRn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="432" y="2064" type="branch" />
<wire x2="432" y1="2064" y2="2064" x1="352" />
<wire x2="512" y1="2064" y2="2064" x1="432" />
</branch>
<branch name="Q0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3296" y="544" type="branch" />
<wire x2="896" y1="832" y2="960" x1="896" />
<wire x2="960" y1="960" y2="960" x1="896" />
<wire x2="896" y1="960" y2="1344" x1="896" />
<wire x2="896" y1="1344" y2="1824" x1="896" />
<wire x2="896" y1="1824" y2="2352" x1="896" />
<wire x2="2768" y1="2352" y2="2352" x1="896" />
<wire x2="1088" y1="1824" y2="1824" x1="896" />
<wire x2="960" y1="1344" y2="1344" x1="896" />
<wire x2="3216" y1="832" y2="832" x1="896" />
<wire x2="3216" y1="544" y2="544" x1="3072" />
<wire x2="3216" y1="544" y2="832" x1="3216" />
<wire x2="3296" y1="544" y2="544" x1="3216" />
<wire x2="3312" y1="544" y2="544" x1="3296" />
<wire x2="3376" y1="544" y2="544" x1="3312" />
</branch>
<branch name="Q1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="960" type="branch" />
<wire x2="3216" y1="1216" y2="1216" x1="928" />
<wire x2="928" y1="1216" y2="1280" x1="928" />
<wire x2="928" y1="1280" y2="1760" x1="928" />
<wire x2="928" y1="1760" y2="2288" x1="928" />
<wire x2="2768" y1="2288" y2="2288" x1="928" />
<wire x2="1088" y1="1760" y2="1760" x1="928" />
<wire x2="960" y1="1280" y2="1280" x1="928" />
<wire x2="3216" y1="960" y2="960" x1="3072" />
<wire x2="3312" y1="960" y2="960" x1="3216" />
<wire x2="3328" y1="960" y2="960" x1="3312" />
<wire x2="3392" y1="960" y2="960" x1="3328" />
<wire x2="3216" y1="960" y2="1216" x1="3216" />
</branch>
<branch name="Q2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3344" y="1344" type="branch" />
<wire x2="1024" y1="1600" y2="1696" x1="1024" />
<wire x2="1088" y1="1696" y2="1696" x1="1024" />
<wire x2="1024" y1="1696" y2="2224" x1="1024" />
<wire x2="2768" y1="2224" y2="2224" x1="1024" />
<wire x2="3232" y1="1600" y2="1600" x1="1024" />
<wire x2="3232" y1="1344" y2="1344" x1="3072" />
<wire x2="3312" y1="1344" y2="1344" x1="3232" />
<wire x2="3344" y1="1344" y2="1344" x1="3312" />
<wire x2="3392" y1="1344" y2="1344" x1="3344" />
<wire x2="3232" y1="1344" y2="1600" x1="3232" />
</branch>
<branch name="Q3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3328" y="1744" type="branch" />
<wire x2="3312" y1="1744" y2="1744" x1="3072" />
<wire x2="3328" y1="1744" y2="1744" x1="3312" />
<wire x2="3392" y1="1744" y2="1744" x1="3328" />
</branch>
<instance x="944" y="512" name="XLXI_33" orien="R0" />
<branch name="LOADn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="384" type="branch" />
<wire x2="496" y1="384" y2="384" x1="416" />
<wire x2="944" y1="384" y2="384" x1="496" />
</branch>
<branch name="XLXN_44">
<wire x2="784" y1="2064" y2="2064" x1="736" />
<wire x2="1456" y1="2064" y2="2064" x1="784" />
<wire x2="784" y1="448" y2="2064" x1="784" />
<wire x2="944" y1="448" y2="448" x1="784" />
<wire x2="1664" y1="720" y2="720" x1="1456" />
<wire x2="1456" y1="720" y2="1136" x1="1456" />
<wire x2="1456" y1="1136" y2="1520" x1="1456" />
<wire x2="1456" y1="1520" y2="2032" x1="1456" />
<wire x2="1456" y1="2032" y2="2064" x1="1456" />
<wire x2="1664" y1="2032" y2="2032" x1="1456" />
<wire x2="1664" y1="1520" y2="1520" x1="1456" />
<wire x2="1664" y1="1136" y2="1136" x1="1456" />
</branch>
<instance x="960" y="1088" name="XLXI_34" orien="R0" />
<branch name="XLXN_45">
<wire x2="1984" y1="992" y2="992" x1="1216" />
</branch>
<branch name="XLXN_50">
<wire x2="1984" y1="1792" y2="1792" x1="1344" />
</branch>
<instance x="1088" y="1952" name="XLXI_36" orien="R0" />
<instance x="432" y="1264" name="XLXI_13" orien="R0" />
<instance x="2768" y="2480" name="XLXI_37" orien="R0" />
<branch name="XLXN_55">
<wire x2="2768" y1="2080" y2="2160" x1="2768" />
<wire x2="3152" y1="2080" y2="2080" x1="2768" />
<wire x2="3152" y1="1872" y2="1872" x1="3072" />
<wire x2="3152" y1="1872" y2="2080" x1="3152" />
</branch>
<instance x="480" y="2400" name="XLXI_38" orien="R0" />
<branch name="CEP">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2272" type="branch" />
<wire x2="304" y1="2272" y2="2272" x1="224" />
<wire x2="480" y1="2272" y2="2272" x1="304" />
</branch>
<branch name="CET">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="304" y="2336" type="branch" />
<wire x2="304" y1="2336" y2="2336" x1="224" />
<wire x2="464" y1="2336" y2="2336" x1="304" />
<wire x2="480" y1="2336" y2="2336" x1="464" />
<wire x2="464" y1="2336" y2="2416" x1="464" />
<wire x2="2768" y1="2416" y2="2416" x1="464" />
</branch>
<branch name="TC">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="2288" type="branch" />
<wire x2="3104" y1="2288" y2="2288" x1="3024" />
<wire x2="3184" y1="2288" y2="2288" x1="3104" />
</branch>
<branch name="P0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="496" y="656" type="branch" />
<wire x2="496" y1="656" y2="656" x1="432" />
<wire x2="512" y1="656" y2="656" x1="496" />
<wire x2="1664" y1="656" y2="656" x1="512" />
</branch>
<branch name="P1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1072" type="branch" />
<wire x2="512" y1="1072" y2="1072" x1="448" />
<wire x2="528" y1="1072" y2="1072" x1="512" />
<wire x2="1664" y1="1072" y2="1072" x1="528" />
</branch>
<instance x="960" y="1472" name="XLXI_35" orien="R0" />
<branch name="XLXN_54">
<wire x2="848" y1="2304" y2="2304" x1="736" />
<wire x2="1984" y1="560" y2="560" x1="848" />
<wire x2="848" y1="560" y2="1024" x1="848" />
<wire x2="960" y1="1024" y2="1024" x1="848" />
<wire x2="848" y1="1024" y2="1408" x1="848" />
<wire x2="960" y1="1408" y2="1408" x1="848" />
<wire x2="848" y1="1408" y2="1888" x1="848" />
<wire x2="1088" y1="1888" y2="1888" x1="848" />
<wire x2="848" y1="1888" y2="2304" x1="848" />
</branch>
<branch name="XLXN_48">
<wire x2="1584" y1="1344" y2="1344" x1="1216" />
<wire x2="1584" y1="1344" y2="1376" x1="1584" />
<wire x2="1984" y1="1376" y2="1376" x1="1584" />
</branch>
<branch name="P2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1456" type="branch" />
<wire x2="512" y1="1456" y2="1456" x1="432" />
<wire x2="1664" y1="1456" y2="1456" x1="512" />
</branch>
<branch name="P3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="1920" type="branch" />
<wire x2="496" y1="1920" y2="1920" x1="416" />
<wire x2="512" y1="1920" y2="1920" x1="496" />
<wire x2="1664" y1="1920" y2="1920" x1="512" />
<wire x2="1664" y1="1904" y2="1920" x1="1664" />
</branch>
<text style="fontsize:24;fontname:Arial" x="2464" y="152">Q0,Q1,Q2,Q3 is Qa,Qb,Qc,Qd from TTL book</text>
<text style="fontsize:24;fontname:Arial" x="3008" y="2168">TC is RCO from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="188" y="2196">CET CEP same as ENT ENP from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="180" y="584">P0 is DATA_A, P1 is DATA_B ... from TTL Book</text>
<text style="fontsize:24;fontname:Arial" x="340" y="308">PEn is LOADn from TTL Book</text>
<iomarker fontsize="28" x="416" y="384" name="LOADn" orien="R180" />
<iomarker fontsize="28" x="432" y="656" name="P0" orien="R180" />
<iomarker fontsize="28" x="448" y="1072" name="P1" orien="R180" />
<iomarker fontsize="28" x="224" y="1232" name="CLK" orien="R180" />
<iomarker fontsize="28" x="432" y="1456" name="P2" orien="R180" />
<iomarker fontsize="28" x="416" y="1920" name="P3" orien="R180" />
<iomarker fontsize="28" x="352" y="2064" name="CLRn" orien="R180" />
<iomarker fontsize="28" x="224" y="2272" name="CEP" orien="R180" />
<iomarker fontsize="28" x="224" y="2336" name="CET" orien="R180" />
<iomarker fontsize="28" x="3376" y="544" name="Q0" orien="R0" />
<iomarker fontsize="28" x="3392" y="960" name="Q1" orien="R0" />
<iomarker fontsize="28" x="3392" y="1344" name="Q2" orien="R0" />
<iomarker fontsize="28" x="3392" y="1744" name="Q3" orien="R0" />
<iomarker fontsize="28" x="3184" y="2288" name="TC" orien="R0" />
</sheet>
</drawing>

10
AppleIIGateSch/chip74LS161.schcmd Normal file
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select figure at 134 1564 8 -branches -sn=1
select figure at 501 353 8 -branches -sn=1
delete selection -sn=1
name branch at 496 384 8 PEn -sn=1
name branch at 512 384 8 PEn -sn=1
select figure at 375 383 8 -branches -sn=1
delete selection -sn=1
select figure at 379 386 8 -branches -sn=1
move bawin at 416 384 to 496 384 -sn=1
add iomarker 416 384 0 Input Unknown -sn=1

51
AppleIIGateSch/chip74LS161.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="chip74LS161">
<symboltype>BLOCK</symboltype>
<timestamp>2018-5-24T4:39:40</timestamp>
<pin polarity="Input" x="384" y="-32" name="CEP" />
<pin polarity="Input" x="0" y="-32" name="CET" />
<pin polarity="Input" x="384" y="-96" name="CLK" />
<pin polarity="Input" x="0" y="-96" name="CLRn" />
<pin polarity="Input" x="384" y="-224" name="P0" />
<pin polarity="Input" x="384" y="-288" name="P1" />
<pin polarity="Input" x="384" y="-352" name="P2" />
<pin polarity="Input" x="384" y="-416" name="P3" />
<pin polarity="Input" x="384" y="-160" name="PEn" />
<pin polarity="Output" x="0" y="-224" name="Q0" />
<pin polarity="Output" x="0" y="-288" name="Q1" />
<pin polarity="Output" x="0" y="-352" name="Q2" />
<pin polarity="Output" x="0" y="-416" name="Q3" />
<pin polarity="Output" x="0" y="-480" name="TC" />
<graph>
<rect width="256" x="64" y="-512" height="512" />
<line x2="384" y1="-32" y2="-32" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin CEP" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin CET" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin CLK" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin CLRn" />
<line x2="384" y1="-224" y2="-224" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin P0" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin P1" />
<line x2="384" y1="-352" y2="-352" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin P2" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin P3" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin PEn" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin Q0" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin Q1" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin Q2" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin Q3" />
<attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="196" y="-428" type="symbol" />
<line x2="0" y1="-480" y2="-480" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin TC" />
</graph>
</symbol>

3
AppleIIGateSch/chip74LS161_guide.ncd Normal file
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104
AppleIIGateSch/chip74LS161_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS161.sch - Wed May 23 13:17:20 2018
`timescale 1ns / 1ps
module chip74LS161_chip74LS161_sch_tb();
// Inputs
reg CLK;
reg CLRn;
reg PEn;
reg CEP;
reg CET;
reg P0;
reg P1;
reg P2;
reg P3;
// Output
wire Q1;
wire Q2;
wire Q3;
wire TC;
wire Q0;
// testbench Vars
integer i;
// Bidirs
// Instantiate the UUT
chip74LS161 UUT (
.CLK(CLK),
.CLRn(CLRn),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3),
.TC(TC),
.PEn(PEn),
.CEP(CEP),
.CET(CET),
.P0(P0),
.P1(P1),
.P2(P2),
.P3(P3)
);
// Initialize Inputs
//`ifdef auto_init
initial begin
CLK = 0;
CLRn = 0;
PEn = 0;
CEP = 0;
CET = 0;
P0 = 0;
P1 = 0;
P2 = 0;
P3 = 0;
//`endif
#100;
#2 CLRn = 1; #2 CLRn=0; #2 CLRn=1;
#2; CLK=1; #1;
CEP=1;
CET=1;
PEn = 1;
for (i=0; i<40; i=i+1) begin
CLK=0; #2;
CLK=1; #2;
end
#4;
CLK=0; #2;
CLK=1; #2;
P0 = 1;
P1 = 1;
P2 = 1;
P3 = 1;
PEn = 1;
CLK=0; #2;
CLK=1; #2;
PEn = 0;
CLK=0; #2;
CLK=1; #2;
PEn = 1;
for (i=0; i<8; i=i+1) begin
CLK=0; #2;
CLK=1; #2;
end
#4;
P0 = 0;
P1 = 1;
P2 = 1;
P3 = 0;
PEn = 0;
CLK=0; #2;
CLK=1; #2;
PEn = 1;
for (i=0; i<8; i=i+1) begin
CLK=0; #2;
CLK=1; #2;
end
end
endmodule

2
AppleIIGateSch/chip74LS175.cmd_log Normal file
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sch2hdl -intstyle ise -family spartan3e -verilog chip74LS175_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS175.sch
sch2verilog -intstyle ise -family spartan3e -tionly {} -tiext tfi -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS175.sch chip74LS175.tfi

1
AppleIIGateSch/chip74LS175.jhd Normal file
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MODULE chip74LS175

235
AppleIIGateSch/chip74LS175.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3e" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="Q0" />
<signal name="Q0n" />
<signal name="Q3" />
<signal name="Q2" />
<signal name="Q1" />
<signal name="Q1n" />
<signal name="Q2n" />
<signal name="Q3n" />
<signal name="D0" />
<signal name="D1" />
<signal name="D2" />
<signal name="D3" />
<signal name="CP" />
<signal name="XLXN_19" />
<signal name="CLRn" />
<port polarity="Output" name="Q0" />
<port polarity="Output" name="Q0n" />
<port polarity="Output" name="Q3" />
<port polarity="Output" name="Q2" />
<port polarity="Output" name="Q1" />
<port polarity="Output" name="Q1n" />
<port polarity="Output" name="Q2n" />
<port polarity="Output" name="Q3n" />
<port polarity="Input" name="D0" />
<port polarity="Input" name="D1" />
<port polarity="Input" name="D2" />
<port polarity="Input" name="D3" />
<port polarity="Input" name="CP" />
<port polarity="Input" name="CLRn" />
<blockdef name="fdc">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<rect width="256" x="64" y="-320" height="256" />
<line x2="80" y1="-112" y2="-128" x1="64" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<line x2="192" y1="-64" y2="-32" x1="192" />
<line x2="64" y1="-32" y2="-32" x1="192" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
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<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<block symbolname="fdc" name="XLXI_1">
<blockpin signalname="CP" name="C" />
<blockpin signalname="XLXN_19" name="CLR" />
<blockpin signalname="D0" name="D" />
<blockpin signalname="Q0" name="Q" />
</block>
<block symbolname="fdc" name="XLXI_2">
<blockpin signalname="CP" name="C" />
<blockpin signalname="XLXN_19" name="CLR" />
<blockpin signalname="D1" name="D" />
<blockpin signalname="Q1" name="Q" />
</block>
<block symbolname="fdc" name="XLXI_3">
<blockpin signalname="CP" name="C" />
<blockpin signalname="XLXN_19" name="CLR" />
<blockpin signalname="D2" name="D" />
<blockpin signalname="Q2" name="Q" />
</block>
<block symbolname="fdc" name="XLXI_4">
<blockpin signalname="CP" name="C" />
<blockpin signalname="XLXN_19" name="CLR" />
<blockpin signalname="D3" name="D" />
<blockpin signalname="Q3" name="Q" />
</block>
<block symbolname="inv" name="XLXI_5">
<blockpin signalname="Q0" name="I" />
<blockpin signalname="Q0n" name="O" />
</block>
<block symbolname="inv" name="XLXI_6">
<blockpin signalname="Q1" name="I" />
<blockpin signalname="Q1n" name="O" />
</block>
<block symbolname="inv" name="XLXI_7">
<blockpin signalname="Q2" name="I" />
<blockpin signalname="Q2n" name="O" />
</block>
<block symbolname="inv" name="XLXI_8">
<blockpin signalname="Q3" name="I" />
<blockpin signalname="Q3n" name="O" />
</block>
<block symbolname="inv" name="XLXI_9">
<blockpin signalname="CLRn" name="I" />
<blockpin signalname="XLXN_19" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2320" y="928" name="XLXI_1" orien="R0" />
<instance x="2320" y="1344" name="XLXI_2" orien="R0" />
<instance x="2320" y="1728" name="XLXI_3" orien="R0" />
<instance x="2320" y="2096" name="XLXI_4" orien="R0" />
<instance x="2832" y="832" name="XLXI_5" orien="R0" />
<branch name="Q0">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3088" y="672" type="branch" />
<wire x2="2768" y1="672" y2="672" x1="2704" />
<wire x2="2768" y1="672" y2="800" x1="2768" />
<wire x2="2832" y1="800" y2="800" x1="2768" />
<wire x2="3088" y1="672" y2="672" x1="2768" />
<wire x2="3152" y1="672" y2="672" x1="3088" />
</branch>
<branch name="Q0n">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3088" y="800" type="branch" />
<wire x2="3088" y1="800" y2="800" x1="3056" />
<wire x2="3152" y1="800" y2="800" x1="3088" />
</branch>
<instance x="2832" y="1248" name="XLXI_6" orien="R0" />
<instance x="2832" y="1632" name="XLXI_7" orien="R0" />
<branch name="Q3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1840" type="branch" />
<wire x2="2752" y1="1840" y2="1840" x1="2704" />
<wire x2="3104" y1="1840" y2="1840" x1="2752" />
<wire x2="3168" y1="1840" y2="1840" x1="3104" />
<wire x2="2752" y1="1840" y2="1984" x1="2752" />
<wire x2="2832" y1="1984" y2="1984" x1="2752" />
</branch>
<branch name="Q2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3104" y="1472" type="branch" />
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56
AppleIIGateSch/chip74LS175.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="chip74LS175">
<symboltype>BLOCK</symboltype>
<timestamp>2018-5-27T1:40:50</timestamp>
<pin polarity="Input" x="0" y="-416" name="CLRn" />
<pin polarity="Input" x="0" y="-480" name="CP" />
<pin polarity="Input" x="0" y="-160" name="D0" />
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2
AppleIIGateSch/chip74LS175_beh.prj Normal file
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verilog work "chip74LS175.vf"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"

104
AppleIIGateSch/chip74LS175_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS175.sch - Thu May 24 17:45:09 2018
`timescale 1ns / 1ps
module chip74LS175_chip74LS175_sch_tb();
// Inputs
reg D0;
reg D1;
reg D2;
reg D3;
reg CP;
reg CLRn;
// Output
wire Q0;
wire Q0n;
wire Q3;
wire Q2;
wire Q1;
wire Q1n;
wire Q2n;
wire Q3n;
wire [3:0] Qbus = {Q3,Q2,Q1,Q0};
wire [3:0] Qbusn = {Q3n,Q2n,Q1n,Q0n};
// TB
integer i;
integer errcnt;
// Bidirs
// Instantiate the UUT
chip74LS175 UUT (
.Q0(Q0),
.Q0n(Q0n),
.Q3(Q3),
.Q2(Q2),
.Q1(Q1),
.Q1n(Q1n),
.Q2n(Q2n),
.Q3n(Q3n),
.D0(D0),
.D1(D1),
.D2(D2),
.D3(D3),
.CP(CP),
.CLRn(CLRn)
);
// Initialize Inputs
// `ifndef auto_init
initial begin
$display("auto_init not set");
#100;
D0 = 0;
D1 = 0;
D2 = 0;
D3 = 0;
CP = 0;
CLRn = 0;
errcnt = 0;
#5;
CLRn = 1;
#5;
for (i=0; i<16; i=i+1) begin
CLRn = 1;
{D3,D2,D1,D0} = i[3:0];
CP = 0; #5; CP = 1; #5;
if ( Qbus != i[3:0] ) begin
$display("Wrong answer i=%d Qbus=%d", i[3:0], Qbus);
errcnt = errcnt + 1;
end
if ( Qbusn != ~i[3:0] ) begin
$display("Wrong answer i=%d ~Qbus=%d", i[3:0], ~Qbus);
errcnt = errcnt + 1;
end
//CP = 0; #5; CP = 1; #5;
//if ( Qbus != (i[3:0]+1) ) begin
// $display("Wrong answer i=%d Qbus=%d", i[3:0]+1, Qbus);
//end
CLRn = 0; CP = 0; #5; CP = 1; #5;
if ( Qbus != 0 ) begin
$display("Wrong answer i=%d CLRn=0 Qbus=%d should be zero", i[3:0]+1, Qbus);
errcnt = errcnt + 1;
end
if ( Qbusn != 4'hf ) begin
$display("Wrong answer i=%d CLRn=0 Qbusn=%d should be 15. ~0", i[3:0]+1, Qbusn);
errcnt = errcnt + 1;
end
end
if ( errcnt == 0 ) begin
$display("**** PASSED **** errcnt=0");
end else begin
$display("!!!! FAILED !!!! errcnt=%d", errcnt);
end
end
// `else begin
// initial begin
// $display("SET auto_init");
// end
// end
// `endif
endmodule

1
AppleIIGateSch/chip74LS257.jhd Normal file
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MODULE chip74LS257

398
AppleIIGateSch/chip74LS257.sch Normal file
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<signal name="Za_4" />
<signal name="Zb_7" />
<signal name="Zc_9" />
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<port polarity="Input" name="En_15" />
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<blockpin signalname="Zd_12" name="O" />
</block>
<block symbolname="inv" name="XLXI_17">
<blockpin signalname="En_15" name="I" />
<blockpin signalname="XLXN_15" name="O" />
</block>
<block symbolname="inv" name="XLXI_18">
<blockpin signalname="XLXN_20" name="I" />
<blockpin signalname="XLXN_17" name="O" />
</block>
<block symbolname="inv" name="XLXI_19">
<blockpin signalname="S_1" name="I" />
<blockpin signalname="XLXN_20" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2528" y="944" name="XLXI_1" orien="R0" />
<instance x="2528" y="1232" name="XLXI_2" orien="R0" />
<instance x="2528" y="1824" name="XLXI_4" orien="R0" />
<instance x="2160" y="1168" name="XLXI_7" orien="R0" />
<instance x="2160" y="1296" name="XLXI_8" orien="R0" />
<instance x="2160" y="1472" name="XLXI_9" orien="R0" />
<instance x="2160" y="1600" name="XLXI_10" orien="R0" />
<instance x="2160" y="1760" name="XLXI_11" orien="R0" />
<instance x="2160" y="1888" name="XLXI_12" orien="R0" />
<instance x="2160" y="1008" name="XLXI_6" orien="R0" />
<instance x="2160" y="880" name="XLXI_5" orien="R0" />
<instance x="2528" y="1536" name="XLXI_3" orien="R0" />
<branch name="XLXN_1">
<wire x2="2464" y1="784" y2="784" x1="2416" />
<wire x2="2464" y1="784" y2="816" x1="2464" />
<wire x2="2528" y1="816" y2="816" x1="2464" />
</branch>
<branch name="XLXN_2">
<wire x2="2464" y1="912" y2="912" x1="2416" />
<wire x2="2464" y1="880" y2="912" x1="2464" />
<wire x2="2528" y1="880" y2="880" x1="2464" />
</branch>
<branch name="XLXN_3">
<wire x2="2464" y1="1072" y2="1072" x1="2416" />
<wire x2="2464" y1="1072" y2="1104" x1="2464" />
<wire x2="2528" y1="1104" y2="1104" x1="2464" />
</branch>
<branch name="XLXN_4">
<wire x2="2464" y1="1200" y2="1200" x1="2416" />
<wire x2="2464" y1="1168" y2="1200" x1="2464" />
<wire x2="2528" y1="1168" y2="1168" x1="2464" />
</branch>
<branch name="XLXN_5">
<wire x2="2464" y1="1376" y2="1376" x1="2416" />
<wire x2="2464" y1="1376" y2="1408" x1="2464" />
<wire x2="2528" y1="1408" y2="1408" x1="2464" />
</branch>
<branch name="XLXN_6">
<wire x2="2464" y1="1504" y2="1504" x1="2416" />
<wire x2="2464" y1="1472" y2="1504" x1="2464" />
<wire x2="2528" y1="1472" y2="1472" x1="2464" />
</branch>
<branch name="XLXN_7">
<wire x2="2464" y1="1664" y2="1664" x1="2416" />
<wire x2="2464" y1="1664" y2="1696" x1="2464" />
<wire x2="2528" y1="1696" y2="1696" x1="2464" />
</branch>
<branch name="XLXN_8">
<wire x2="2464" y1="1792" y2="1792" x1="2416" />
<wire x2="2464" y1="1760" y2="1792" x1="2464" />
<wire x2="2528" y1="1760" y2="1760" x1="2464" />
</branch>
<instance x="2848" y="1168" name="XLXI_13" orien="R0" />
<instance x="2848" y="880" name="XLXI_14" orien="R0" />
<instance x="2848" y="1472" name="XLXI_15" orien="R0" />
<instance x="2848" y="1760" name="XLXI_16" orien="R0" />
<branch name="XLXN_9">
<wire x2="2848" y1="848" y2="848" x1="2784" />
</branch>
<branch name="XLXN_10">
<wire x2="2848" y1="1136" y2="1136" x1="2784" />
</branch>
<branch name="XLXN_11">
<wire x2="2848" y1="1440" y2="1440" x1="2784" />
</branch>
<branch name="XLXN_12">
<wire x2="2848" y1="1728" y2="1728" x1="2784" />
</branch>
<branch name="XLXN_15">
<wire x2="2832" y1="608" y2="608" x1="1760" />
<wire x2="2832" y1="608" y2="784" x1="2832" />
<wire x2="2848" y1="784" y2="784" x1="2832" />
<wire x2="2832" y1="784" y2="1072" x1="2832" />
<wire x2="2848" y1="1072" y2="1072" x1="2832" />
<wire x2="2832" y1="1072" y2="1376" x1="2832" />
<wire x2="2848" y1="1376" y2="1376" x1="2832" />
<wire x2="2832" y1="1376" y2="1664" x1="2832" />
<wire x2="2848" y1="1664" y2="1664" x1="2832" />
</branch>
<instance x="1536" y="640" name="XLXI_17" orien="R0" />
<branch name="En_15">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="608" type="branch" />
<wire x2="1328" y1="608" y2="608" x1="1280" />
<wire x2="1536" y1="608" y2="608" x1="1328" />
</branch>
<iomarker fontsize="28" x="1280" y="608" name="En_15" orien="R180" />
<text style="fontsize:20;fontname:Arial" x="1296" y="544">Gn instead of En in TTL Bookr</text>
<branch name="XLXN_17">
<wire x2="2080" y1="1968" y2="1968" x1="2064" />
<wire x2="2160" y1="944" y2="944" x1="2080" />
<wire x2="2080" y1="944" y2="1232" x1="2080" />
<wire x2="2160" y1="1232" y2="1232" x1="2080" />
<wire x2="2080" y1="1232" y2="1536" x1="2080" />
<wire x2="2160" y1="1536" y2="1536" x1="2080" />
<wire x2="2080" y1="1536" y2="1824" x1="2080" />
<wire x2="2160" y1="1824" y2="1824" x1="2080" />
<wire x2="2080" y1="1824" y2="1968" x1="2080" />
</branch>
<branch name="XLXN_20">
<wire x2="1824" y1="1968" y2="1968" x1="1792" />
<wire x2="1840" y1="1968" y2="1968" x1="1824" />
<wire x2="1824" y1="816" y2="1104" x1="1824" />
<wire x2="1824" y1="1104" y2="1408" x1="1824" />
<wire x2="1824" y1="1408" y2="1696" x1="1824" />
<wire x2="2160" y1="1696" y2="1696" x1="1824" />
<wire x2="1824" y1="1696" y2="1968" x1="1824" />
<wire x2="2160" y1="1408" y2="1408" x1="1824" />
<wire x2="2160" y1="1104" y2="1104" x1="1824" />
<wire x2="2160" y1="816" y2="816" x1="1824" />
</branch>
<instance x="1840" y="2000" name="XLXI_18" orien="R0" />
<instance x="1568" y="2000" name="XLXI_19" orien="R0" />
<branch name="S_1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1264" y="1968" type="branch" />
<wire x2="1264" y1="1968" y2="1968" x1="1216" />
<wire x2="1568" y1="1968" y2="1968" x1="1264" />
</branch>
<iomarker fontsize="28" x="1216" y="1968" name="S_1" orien="R180" />
<text style="fontsize:20;fontname:Arial" x="1248" y="1996">An/B instead of S in TTL Book</text>
<branch name="i0a_2">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="752" type="branch" />
<wire x2="1360" y1="752" y2="752" x1="1296" />
<wire x2="2160" y1="752" y2="752" x1="1360" />
</branch>
<branch name="i1a_3">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="880" type="branch" />
<wire x2="1344" y1="880" y2="880" x1="1296" />
<wire x2="2160" y1="880" y2="880" x1="1344" />
</branch>
<branch name="i0b_5">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1040" type="branch" />
<wire x2="1344" y1="1040" y2="1040" x1="1296" />
<wire x2="2160" y1="1040" y2="1040" x1="1344" />
</branch>
<branch name="i1b_6">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="1168" type="branch" />
<wire x2="1328" y1="1168" y2="1168" x1="1296" />
<wire x2="2160" y1="1168" y2="1168" x1="1328" />
</branch>
<branch name="i0c_11">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1344" type="branch" />
<wire x2="1344" y1="1344" y2="1344" x1="1296" />
<wire x2="2160" y1="1344" y2="1344" x1="1344" />
</branch>
<branch name="i1c_10">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1328" y="1472" type="branch" />
<wire x2="1328" y1="1472" y2="1472" x1="1296" />
<wire x2="2160" y1="1472" y2="1472" x1="1328" />
</branch>
<branch name="i0d_14">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="1632" type="branch" />
<wire x2="1360" y1="1632" y2="1632" x1="1296" />
<wire x2="2160" y1="1632" y2="1632" x1="1360" />
</branch>
<branch name="i1d_13">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="1760" type="branch" />
<wire x2="1344" y1="1760" y2="1760" x1="1296" />
<wire x2="2160" y1="1760" y2="1760" x1="1344" />
</branch>
<iomarker fontsize="28" x="1296" y="752" name="i0a_2" orien="R180" />
<iomarker fontsize="28" x="1296" y="880" name="i1a_3" orien="R180" />
<iomarker fontsize="28" x="1296" y="1040" name="i0b_5" orien="R180" />
<iomarker fontsize="28" x="1296" y="1168" name="i1b_6" orien="R180" />
<iomarker fontsize="28" x="1296" y="1344" name="i0c_11" orien="R180" />
<iomarker fontsize="28" x="1296" y="1472" name="i1c_10" orien="R180" />
<iomarker fontsize="28" x="1296" y="1632" name="i0d_14" orien="R180" />
<iomarker fontsize="28" x="1296" y="1760" name="i1d_13" orien="R180" />
<text style="fontsize:20;fontname:Arial" x="1344" y="776">1A instead of i0a in TTL book</text>
<text style="fontsize:20;fontname:Arial" x="1344" y="900">1B instead of i1a in TTL book</text>
<text style="fontsize:20;fontname:Arial" x="1340" y="1056">2A instead of i0a in TTL book</text>
<text style="fontsize:20;fontname:Arial" x="1352" y="1184">2B instead of i1b in TTL book</text>
<text style="fontsize:20;fontname:Arial" x="1360" y="1368">3A</text>
<text style="fontsize:20;fontname:Arial" x="1368" y="1492">3B</text>
<text style="fontsize:20;fontname:Arial" x="1368" y="1648">4A</text>
<text style="fontsize:20;fontname:Arial" x="1356" y="1780">4B</text>
<branch name="Za_4">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="848" type="branch" />
<wire x2="3168" y1="848" y2="848" x1="3072" />
<wire x2="3248" y1="848" y2="848" x1="3168" />
</branch>
<branch name="Zb_7">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1136" type="branch" />
<wire x2="3168" y1="1136" y2="1136" x1="3072" />
<wire x2="3248" y1="1136" y2="1136" x1="3168" />
</branch>
<branch name="Zc_9">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1440" type="branch" />
<wire x2="3168" y1="1440" y2="1440" x1="3072" />
<wire x2="3232" y1="1440" y2="1440" x1="3168" />
</branch>
<branch name="Zd_12">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="3168" y="1728" type="branch" />
<wire x2="3168" y1="1728" y2="1728" x1="3072" />
<wire x2="3248" y1="1728" y2="1728" x1="3168" />
</branch>
<iomarker fontsize="28" x="3248" y="848" name="Za_4" orien="R0" />
<iomarker fontsize="28" x="3248" y="1136" name="Zb_7" orien="R0" />
<iomarker fontsize="28" x="3232" y="1440" name="Zc_9" orien="R0" />
<iomarker fontsize="28" x="3248" y="1728" name="Zd_12" orien="R0" />
<text style="fontsize:20;fontname:Arial" x="3140" y="888">1Y in TTL book</text>
<text style="fontsize:28;fontname:Arial" x="3160" y="1176">2Y</text>
<text style="fontsize:28;fontname:Arial" x="3160" y="1476">3Y</text>
<text style="fontsize:28;fontname:Arial" x="3168" y="1756">4Y</text>
</sheet>
</drawing>

52
AppleIIGateSch/chip74LS257.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="chip74LS257">
<symboltype>BLOCK</symboltype>
<timestamp>2018-6-7T7:8:22</timestamp>
<pin polarity="Input" x="0" y="-544" name="i0a_2" />
<pin polarity="Input" x="0" y="-480" name="i0b_5" />
<pin polarity="Input" x="0" y="-416" name="i0c_11" />
<pin polarity="Input" x="0" y="-352" name="i0d_14" />
<pin polarity="Input" x="0" y="-224" name="i1a_3" />
<pin polarity="Input" x="0" y="-160" name="i1b_6" />
<pin polarity="Input" x="0" y="-96" name="i1c_10" />
<pin polarity="Input" x="0" y="-32" name="i1d_13" />
<pin polarity="Input" x="0" y="-288" name="S_1" />
<pin polarity="Input" x="384" y="-32" name="En_15" />
<pin polarity="Output" x="384" y="-416" name="Za_4" />
<pin polarity="Output" x="384" y="-352" name="Zb_7" />
<pin polarity="Output" x="384" y="-288" name="Zc_9" />
<pin polarity="Output" x="384" y="-224" name="Zd_12" />
<graph>
<rect width="256" x="64" y="-576" height="576" />
<attrtext style="alignment:BCENTER;fontsize:40;fontname:Arial" attrname="SymbolName" x="192" y="-584" type="symbol" />
<line x2="0" y1="-544" y2="-544" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-544" type="pin i0a_2" />
<line x2="0" y1="-480" y2="-480" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin i0b_5" />
<line x2="0" y1="-416" y2="-416" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-416" type="pin i0c_11" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin i0d_14" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin i1a_3" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin i1b_6" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin i1c_10" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin i1d_13" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin S_1" />
<line x2="384" y1="-32" y2="-32" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin En_15" />
<line x2="384" y1="-416" y2="-416" x1="320" />
<line x2="384" y1="-352" y2="-352" x1="320" />
<line x2="384" y1="-288" y2="-288" x1="320" />
<line x2="384" y1="-224" y2="-224" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin Za_4" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin Zb_7" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin Zc_9" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin Zd_12" />
<circle r="10" cx="330" cy="-32" />
</graph>
</symbol>

104
AppleIIGateSch/chip74LS257_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS257.sch - Wed Jun 06 16:37:03 2018
`timescale 1ns / 1ps
module chip74LS257_chip74LS257_sch_tb();
// Inputs
reg En_15;
reg S_1;
reg i0a_2;
reg i1a_3;
reg i0b_5;
reg i1b_6;
reg i0c_11;
reg i1c_10;
reg i0d_14;
reg i1d_13;
// Output
wire Za_4;
wire Zb_7;
wire Zc_9;
wire Zd_12;
// Bidirs
wire expectedA, expectedB, expectedC, expectedD;
// Instantiate the UUT
chip74LS257 UUT (
.En_15(En_15),
.S_1(S_1),
.i0a_2(i0a_2),
.i1a_3(i1a_3),
.i0b_5(i0b_5),
.i1b_6(i1b_6),
.i0c_11(i0c_11),
.i1c_10(i1c_10),
.i0d_14(i0d_14),
.i1d_13(i1d_13),
.Za_4(Za_4),
.Zb_7(Zb_7),
.Zc_9(Zc_9),
.Zd_12(Zd_12)
);
// Test Sim
integer i, errct;
assign expectedA = En_15 ? 1'bx : (S_1 ? i1a_3 : i0a_2 );
assign expectedB = En_15 ? 1'bx : (S_1 ? i1b_6 : i0b_5 );
assign expectedC = En_15 ? 1'bx : (S_1 ? i1c_10 : i0c_11);
assign expectedD = En_15 ? 1'bx : (S_1 ? i1d_13 : i0d_14);
// Initialize Inputs
`ifdef auto_init
initial begin
$display("auto_init defined");
end
`else
initial begin
$display("auto_init not defined");
end
`endif
initial begin
En_15 = 0;
S_1 = 0;
i0a_2 = 0;
i1a_3 = 0;
i0b_5 = 0;
i1b_6 = 0;
i0c_11 = 0;
i1c_10 = 0;
i0d_14 = 0;
i1d_13 = 0;
errct = 0;
#100;
for (i=0; i<1024; i=i+1) begin
{En_15, S_1, i1d_13,i1c_10,i1b_6,i1a_3, i0d_14,i0c_11,i0b_5,i0a_2} = i;
#9;
if ( Za_4 != expectedA ) begin
$display("i:%d Za_4=%b expectedA=%b", i, Za_4, expectedA);
errct = errct + 1;
end
if ( Zb_7 != expectedB ) begin
$display("i:%d Zb_7=%b expectedB=%b", i, Zb_7, expectedB);
errct = errct + 1;
end
if ( Zc_9 != expectedC ) begin
$display("i:%d Zc_9=%b expectedA=%b", i, Zc_9, expectedC);
errct = errct + 1;
end
if ( Zd_12 != expectedD ) begin
$display("i:%d Zd_12=%b expectedD=%b", i, Zd_12, expectedD);
errct = errct + 1;
end
#1;
end
if ( errct==0 ) begin
$display("PASSED");
end else begin
$display("FAILED errct=%d", errct);
end
$finish;
end
endmodule

1
AppleIIGateSch/chip74S195.cmd_log Normal file
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sch2hdl -intstyle ise -family spartan3e -verilog chip74S195.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74S195.sch

1
AppleIIGateSch/chip74S195.jhd Normal file
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MODULE chip74S195

547
AppleIIGateSch/chip74S195.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3e" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="XLXN_3" />
<signal name="CLRn_1" />
<signal name="XLXN_9" />
<signal name="XLXN_11" />
<signal name="XLXN_12" />
<signal name="XLXN_13" />
<signal name="CP_10" />
<signal name="XLXN_17" />
<signal name="XLXN_19" />
<signal name="XLXN_20" />
<signal name="XLXN_21" />
<signal name="XLXN_22" />
<signal name="XLXN_23" />
<signal name="XLXN_24" />
<signal name="XLXN_25" />
<signal name="XLXN_26" />
<signal name="XLXN_27" />
<signal name="XLXN_28" />
<signal name="XLXN_29" />
<signal name="XLXN_30" />
<signal name="XLXN_32" />
<signal name="SH_LDn" />
<signal name="XLXN_37" />
<signal name="XLXN_38" />
<signal name="Q0_15" />
<signal name="J_2" />
<signal name="K_3" />
<signal name="XLXN_49" />
<signal name="P0_4" />
<signal name="P1_5" />
<signal name="P2_6" />
<signal name="P3_7" />
<signal name="Q1_14" />
<signal name="Q2_13" />
<signal name="Q3_12" />
<signal name="Q3n_11" />
<port polarity="Input" name="CLRn_1" />
<port polarity="Input" name="CP_10" />
<port polarity="Input" name="SH_LDn" />
<port polarity="Output" name="Q0_15" />
<port polarity="Input" name="J_2" />
<port polarity="Input" name="K_3" />
<port polarity="Input" name="P0_4" />
<port polarity="Input" name="P1_5" />
<port polarity="Input" name="P2_6" />
<port polarity="Input" name="P3_7" />
<port polarity="Output" name="Q1_14" />
<port polarity="Output" name="Q2_13" />
<port polarity="Output" name="Q3_12" />
<port polarity="Output" name="Q3n_11" />
<blockdef name="fjkc">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="64" y1="-320" y2="-320" x1="0" />
<line x2="320" y1="-256" y2="-256" x1="384" />
<line x2="64" y1="-256" y2="-256" x1="0" />
<line x2="64" y1="-32" y2="-32" x1="192" />
<line x2="192" y1="-64" y2="-32" x1="192" />
<line x2="64" y1="-128" y2="-144" x1="80" />
<line x2="80" y1="-112" y2="-128" x1="64" />
<rect width="256" x="64" y="-384" height="320" />
</blockdef>
<blockdef name="inv">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="160" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="-64" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="0" x1="128" />
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
<blockdef name="nor3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="48" y1="-64" y2="-64" x1="0" />
<line x2="72" y1="-128" y2="-128" x1="0" />
<line x2="48" y1="-192" y2="-192" x1="0" />
<line x2="216" y1="-128" y2="-128" x1="256" />
<circle r="12" cx="204" cy="-128" />
<line x2="48" y1="-64" y2="-80" x1="48" />
<line x2="48" y1="-192" y2="-176" x1="48" />
<line x2="48" y1="-80" y2="-80" x1="112" />
<line x2="48" y1="-176" y2="-176" x1="112" />
<arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
<arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
<arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
</blockdef>
<blockdef name="and3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="64" y1="-192" y2="-192" x1="0" />
<line x2="192" y1="-128" y2="-128" x1="256" />
<line x2="144" y1="-176" y2="-176" x1="64" />
<line x2="64" y1="-80" y2="-80" x1="144" />
<arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
<line x2="64" y1="-64" y2="-192" x1="64" />
</blockdef>
<blockdef name="and2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="192" y1="-96" y2="-96" x1="256" />
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
<line x2="64" y1="-48" y2="-48" x1="144" />
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
<blockdef name="nor2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
<line x2="64" y1="-128" y2="-128" x1="0" />
<line x2="216" y1="-96" y2="-96" x1="256" />
<circle r="12" cx="204" cy="-96" />
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
<line x2="48" y1="-48" y2="-48" x1="112" />
<line x2="48" y1="-144" y2="-144" x1="112" />
</blockdef>
<block symbolname="fjkc" name="XLXI_6">
<blockpin signalname="XLXN_17" name="C" />
<blockpin signalname="XLXN_3" name="CLR" />
<blockpin signalname="XLXN_27" name="J" />
<blockpin signalname="XLXN_28" name="K" />
<blockpin signalname="Q3_12" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_17">
<blockpin signalname="XLXN_17" name="C" />
<blockpin signalname="XLXN_3" name="CLR" />
<blockpin signalname="XLXN_23" name="J" />
<blockpin signalname="XLXN_24" name="K" />
<blockpin signalname="Q2_13" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_18">
<blockpin signalname="XLXN_17" name="C" />
<blockpin signalname="XLXN_3" name="CLR" />
<blockpin signalname="XLXN_9" name="J" />
<blockpin signalname="XLXN_38" name="K" />
<blockpin signalname="Q0_15" name="Q" />
</block>
<block symbolname="fjkc" name="XLXI_19">
<blockpin signalname="XLXN_17" name="C" />
<blockpin signalname="XLXN_3" name="CLR" />
<blockpin signalname="XLXN_19" name="J" />
<blockpin signalname="XLXN_20" name="K" />
<blockpin signalname="Q1_14" name="Q" />
</block>
<block symbolname="inv" name="XLXI_21">
<blockpin signalname="CLRn_1" name="I" />
<blockpin signalname="XLXN_3" name="O" />
</block>
<block symbolname="inv" name="XLXI_22">
<blockpin signalname="XLXN_38" name="I" />
<blockpin signalname="XLXN_9" name="O" />
</block>
<block symbolname="nor3" name="XLXI_23">
<blockpin signalname="XLXN_13" name="I0" />
<blockpin signalname="XLXN_12" name="I1" />
<blockpin signalname="XLXN_11" name="I2" />
<blockpin signalname="XLXN_38" name="O" />
</block>
<block symbolname="and3" name="XLXI_24">
<blockpin signalname="XLXN_32" name="I0" />
<blockpin signalname="K_3" name="I1" />
<blockpin signalname="Q0_15" name="I2" />
<blockpin signalname="XLXN_12" name="O" />
</block>
<block symbolname="and3" name="XLXI_25">
<blockpin signalname="XLXN_37" name="I0" />
<blockpin signalname="J_2" name="I1" />
<blockpin signalname="XLXN_32" name="I2" />
<blockpin signalname="XLXN_13" name="O" />
</block>
<block symbolname="and2" name="XLXI_26">
<blockpin signalname="XLXN_49" name="I0" />
<blockpin signalname="P0_4" name="I1" />
<blockpin signalname="XLXN_11" name="O" />
</block>
<block symbolname="and2" name="XLXI_27">
<blockpin signalname="CP_10" name="I0" />
<blockpin signalname="CLRn_1" name="I1" />
<blockpin signalname="XLXN_17" name="O" />
</block>
<block symbolname="inv" name="XLXI_28">
<blockpin signalname="XLXN_20" name="I" />
<blockpin signalname="XLXN_19" name="O" />
</block>
<block symbolname="and2" name="XLXI_30">
<blockpin signalname="XLXN_49" name="I0" />
<blockpin signalname="P1_5" name="I1" />
<blockpin signalname="XLXN_22" name="O" />
</block>
<block symbolname="and2" name="XLXI_31">
<blockpin signalname="Q0_15" name="I0" />
<blockpin signalname="XLXN_32" name="I1" />
<blockpin signalname="XLXN_21" name="O" />
</block>
<block symbolname="nor2" name="XLXI_32">
<blockpin signalname="XLXN_21" name="I0" />
<blockpin signalname="XLXN_22" name="I1" />
<blockpin signalname="XLXN_20" name="O" />
</block>
<block symbolname="inv" name="XLXI_33">
<blockpin signalname="XLXN_24" name="I" />
<blockpin signalname="XLXN_23" name="O" />
</block>
<block symbolname="nor2" name="XLXI_34">
<blockpin signalname="XLXN_26" name="I0" />
<blockpin signalname="XLXN_25" name="I1" />
<blockpin signalname="XLXN_24" name="O" />
</block>
<block symbolname="and2" name="XLXI_35">
<blockpin signalname="Q1_14" name="I0" />
<blockpin signalname="XLXN_32" name="I1" />
<blockpin signalname="XLXN_26" name="O" />
</block>
<block symbolname="and2" name="XLXI_36">
<blockpin signalname="XLXN_49" name="I0" />
<blockpin signalname="P2_6" name="I1" />
<blockpin signalname="XLXN_25" name="O" />
</block>
<block symbolname="and2" name="XLXI_37">
<blockpin signalname="Q2_13" name="I0" />
<blockpin signalname="XLXN_32" name="I1" />
<blockpin signalname="XLXN_30" name="O" />
</block>
<block symbolname="and2" name="XLXI_38">
<blockpin signalname="XLXN_49" name="I0" />
<blockpin signalname="P3_7" name="I1" />
<blockpin signalname="XLXN_29" name="O" />
</block>
<block symbolname="nor2" name="XLXI_39">
<blockpin signalname="XLXN_30" name="I0" />
<blockpin signalname="XLXN_29" name="I1" />
<blockpin signalname="XLXN_28" name="O" />
</block>
<block symbolname="inv" name="XLXI_40">
<blockpin signalname="XLXN_28" name="I" />
<blockpin signalname="XLXN_27" name="O" />
</block>
<block symbolname="inv" name="XLXI_41">
<blockpin signalname="XLXN_49" name="I" />
<blockpin signalname="XLXN_32" name="O" />
</block>
<block symbolname="inv" name="XLXI_42">
<blockpin signalname="SH_LDn" name="I" />
<blockpin signalname="XLXN_49" name="O" />
</block>
<block symbolname="inv" name="XLXI_43">
<blockpin signalname="Q0_15" name="I" />
<blockpin signalname="XLXN_37" name="O" />
</block>
<block symbolname="inv" name="XLXI_44">
<blockpin signalname="Q3_12" name="I" />
<blockpin signalname="Q3n_11" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="2720" y="528" name="XLXI_6" orien="R270" />
<instance x="2720" y="1136" name="XLXI_17" orien="R270" />
<instance x="2720" y="1696" name="XLXI_19" orien="R270" />
<instance x="2720" y="2256" name="XLXI_18" orien="R270" />
<instance x="2832" y="2592" name="XLXI_21" orien="R270" />
<branch name="XLXN_3">
<wire x2="2800" y1="528" y2="528" x1="2688" />
<wire x2="2800" y1="528" y2="1136" x1="2800" />
<wire x2="2800" y1="1136" y2="1696" x1="2800" />
<wire x2="2800" y1="1696" y2="2256" x1="2800" />
<wire x2="2800" y1="2256" y2="2368" x1="2800" />
<wire x2="2800" y1="1136" y2="1136" x1="2688" />
<wire x2="2800" y1="1696" y2="1696" x1="2688" />
<wire x2="2800" y1="2256" y2="2256" x1="2688" />
</branch>
<branch name="CLRn_1">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2736" y="2656" type="branch" />
<wire x2="2736" y1="2656" y2="2656" x1="2672" />
<wire x2="2800" y1="2656" y2="2656" x1="2736" />
<wire x2="2800" y1="2592" y2="2608" x1="2800" />
<wire x2="2912" y1="2608" y2="2608" x1="2800" />
<wire x2="2800" y1="2608" y2="2656" x1="2800" />
<wire x2="2912" y1="2560" y2="2608" x1="2912" />
</branch>
<instance x="2064" y="2336" name="XLXI_22" orien="R0" />
<branch name="XLXN_9">
<wire x2="2400" y1="2304" y2="2304" x1="2288" />
<wire x2="2400" y1="2256" y2="2304" x1="2400" />
</branch>
<instance x="1456" y="2432" name="XLXI_23" orien="R0" />
<instance x="1056" y="2432" name="XLXI_24" orien="R0" />
<instance x="1056" y="2624" name="XLXI_25" orien="R0" />
<instance x="1056" y="2240" name="XLXI_26" orien="R0" />
<branch name="XLXN_11">
<wire x2="1456" y1="2144" y2="2144" x1="1312" />
<wire x2="1456" y1="2144" y2="2240" x1="1456" />
</branch>
<branch name="XLXN_12">
<wire x2="1456" y1="2304" y2="2304" x1="1312" />
</branch>
<branch name="XLXN_13">
<wire x2="1456" y1="2496" y2="2496" x1="1312" />
<wire x2="1456" y1="2368" y2="2496" x1="1456" />
</branch>
<instance x="3040" y="2560" name="XLXI_27" orien="R270" />
<branch name="CP_10">
<attrtext style="alignment:SOFT-TCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2976" y="2688" type="branch" />
<wire x2="2976" y1="2688" y2="2688" x1="2944" />
<wire x2="2976" y1="2560" y2="2688" x1="2976" />
</branch>
<branch name="XLXN_17">
<wire x2="2592" y1="528" y2="576" x1="2592" />
<wire x2="2944" y1="576" y2="576" x1="2592" />
<wire x2="2944" y1="576" y2="1200" x1="2944" />
<wire x2="2944" y1="1200" y2="1776" x1="2944" />
<wire x2="2944" y1="1776" y2="2288" x1="2944" />
<wire x2="2944" y1="2288" y2="2304" x1="2944" />
<wire x2="2592" y1="1136" y2="1200" x1="2592" />
<wire x2="2944" y1="1200" y2="1200" x1="2592" />
<wire x2="2592" y1="1696" y2="1776" x1="2592" />
<wire x2="2944" y1="1776" y2="1776" x1="2592" />
<wire x2="2592" y1="2256" y2="2288" x1="2592" />
<wire x2="2944" y1="2288" y2="2288" x1="2592" />
</branch>
<branch name="XLXN_19">
<wire x2="2400" y1="1728" y2="1728" x1="2288" />
<wire x2="2400" y1="1696" y2="1728" x1="2400" />
</branch>
<instance x="1056" y="1760" name="XLXI_30" orien="R0" />
<instance x="2064" y="1216" name="XLXI_33" orien="R0" />
<branch name="XLXN_23">
<wire x2="2400" y1="1184" y2="1184" x1="2288" />
<wire x2="2400" y1="1136" y2="1184" x1="2400" />
</branch>
<instance x="1472" y="1280" name="XLXI_34" orien="R0" />
<branch name="XLXN_24">
<wire x2="1984" y1="1184" y2="1184" x1="1728" />
<wire x2="2064" y1="1184" y2="1184" x1="1984" />
<wire x2="1984" y1="1184" y2="1232" x1="1984" />
<wire x2="2464" y1="1232" y2="1232" x1="1984" />
<wire x2="2464" y1="1136" y2="1232" x1="2464" />
</branch>
<instance x="1072" y="1360" name="XLXI_35" orien="R0" />
<instance x="1072" y="1200" name="XLXI_36" orien="R0" />
<branch name="XLXN_25">
<wire x2="1392" y1="1104" y2="1104" x1="1328" />
<wire x2="1392" y1="1104" y2="1152" x1="1392" />
<wire x2="1472" y1="1152" y2="1152" x1="1392" />
</branch>
<branch name="XLXN_26">
<wire x2="1392" y1="1264" y2="1264" x1="1328" />
<wire x2="1392" y1="1216" y2="1264" x1="1392" />
<wire x2="1472" y1="1216" y2="1216" x1="1392" />
</branch>
<instance x="1072" y="736" name="XLXI_37" orien="R0" />
<instance x="1072" y="576" name="XLXI_38" orien="R0" />
<instance x="1456" y="656" name="XLXI_39" orien="R0" />
<instance x="2080" y="592" name="XLXI_40" orien="R0" />
<branch name="XLXN_27">
<wire x2="2400" y1="560" y2="560" x1="2304" />
<wire x2="2400" y1="528" y2="560" x1="2400" />
</branch>
<branch name="XLXN_28">
<wire x2="1984" y1="560" y2="560" x1="1712" />
<wire x2="2080" y1="560" y2="560" x1="1984" />
<wire x2="1984" y1="560" y2="608" x1="1984" />
<wire x2="2464" y1="608" y2="608" x1="1984" />
<wire x2="2464" y1="528" y2="608" x1="2464" />
</branch>
<branch name="XLXN_29">
<wire x2="1392" y1="480" y2="480" x1="1328" />
<wire x2="1392" y1="480" y2="528" x1="1392" />
<wire x2="1456" y1="528" y2="528" x1="1392" />
</branch>
<branch name="XLXN_30">
<wire x2="1392" y1="640" y2="640" x1="1328" />
<wire x2="1392" y1="592" y2="640" x1="1392" />
<wire x2="1456" y1="592" y2="592" x1="1392" />
</branch>
<branch name="XLXN_32">
<wire x2="944" y1="2592" y2="2592" x1="848" />
<wire x2="1072" y1="608" y2="608" x1="944" />
<wire x2="944" y1="608" y2="1232" x1="944" />
<wire x2="1072" y1="1232" y2="1232" x1="944" />
<wire x2="944" y1="1232" y2="1760" x1="944" />
<wire x2="944" y1="1760" y2="2368" x1="944" />
<wire x2="944" y1="2368" y2="2432" x1="944" />
<wire x2="1056" y1="2432" y2="2432" x1="944" />
<wire x2="944" y1="2432" y2="2592" x1="944" />
<wire x2="1056" y1="2368" y2="2368" x1="944" />
<wire x2="1056" y1="1760" y2="1760" x1="944" />
</branch>
<instance x="624" y="2624" name="XLXI_41" orien="R0" />
<instance x="352" y="2688" name="XLXI_42" orien="R0" />
<branch name="SH_LDn">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="2656" type="branch" />
<wire x2="320" y1="2656" y2="2656" x1="304" />
<wire x2="352" y1="2656" y2="2656" x1="320" />
</branch>
<iomarker fontsize="28" x="304" y="2656" name="SH_LDn" orien="R180" />
<branch name="XLXN_38">
<wire x2="2000" y1="2304" y2="2304" x1="1712" />
<wire x2="2064" y1="2304" y2="2304" x1="2000" />
<wire x2="2000" y1="2304" y2="2352" x1="2000" />
<wire x2="2464" y1="2352" y2="2352" x1="2000" />
<wire x2="2464" y1="2256" y2="2352" x1="2464" />
</branch>
<instance x="2064" y="1760" name="XLXI_28" orien="R0" />
<instance x="1456" y="1824" name="XLXI_32" orien="R0" />
<branch name="XLXN_22">
<wire x2="1328" y1="1664" y2="1664" x1="1312" />
<wire x2="1328" y1="1664" y2="1696" x1="1328" />
<wire x2="1456" y1="1696" y2="1696" x1="1328" />
</branch>
<branch name="XLXN_21">
<wire x2="1328" y1="1792" y2="1792" x1="1312" />
<wire x2="1328" y1="1760" y2="1792" x1="1328" />
<wire x2="1456" y1="1760" y2="1760" x1="1328" />
</branch>
<branch name="XLXN_20">
<wire x2="1984" y1="1728" y2="1728" x1="1712" />
<wire x2="2064" y1="1728" y2="1728" x1="1984" />
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</drawing>

56
AppleIIGateSch/chip74S195.sym Normal file
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@ -0,0 +1,56 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="chip74S195">
<symboltype>BLOCK</symboltype>
<timestamp>2018-6-3T18:32:16</timestamp>
<pin polarity="Input" x="384" y="-96" name="CLRn_1" />
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<graph>
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</symbol>

108
AppleIIGateSch/chip74S195_tb.v Normal file
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// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74S195.sch - Wed May 30 20:53:58 2018
`timescale 1ns / 1ps
module chip74S195_chip74S195_sch_tb();
// Inputs
reg CLRn_1;
reg CP_10;
reg SH_LDn;
reg J_2;
reg K_3;
reg P0_4;
reg P1_5;
reg P2_6;
reg P3_7;
// Output
wire Q0_15;
wire Q1_14;
wire Q2_13;
wire Q3_12;
wire Q3n_11;
// Bidirs
// simulation vars
integer i, errct;
wire [4:0] qbus = {Q3n_11,Q3_12,Q2_13,Q1_14,Q0_15};
wire [4:0] pbus = {~P3_7,P3_7,P2_6,P1_5,P0_4};
// Instantiate the UUT
chip74S195 UUT (
.CLRn_1(CLRn_1),
.CP_10(CP_10),
.SH_LDn(SH_LDn),
.J_2(J_2),
.K_3(K_3),
.P0_4(P0_4),
.P1_5(P1_5),
.P2_6(P2_6),
.P3_7(P3_7),
.Q0_15(Q0_15),
.Q1_14(Q1_14),
.Q2_13(Q2_13),
.Q3_12(Q3_12),
.Q3n_11(Q3n_11)
);
// Initialize Inputs
`ifdef auto_init
initial begin
$display("auto_init defined");
end
`else
initial begin
$display("not defined auto_init");
end
`endif
initial begin
CLRn_1 = 0;
CP_10 = 0;
SH_LDn = 0;
J_2 = 0;
K_3 = 0;
P0_4 = 0;
P1_5 = 0;
P2_6 = 0;
P3_7 = 0;
errct = 0;
#105
CLRn_1 = 1;
#5
for (i=0; i<16; i=i+1) begin
{P3_7,P2_6,P1_5,P0_4} = i[3:0];
CP_10 = 0;
#5
CP_10 = 1;
#5;
if ( qbus!= pbus ) begin
errct = errct + 1;
$display("ERROR: qbus=%b != pbus=%b", qbus, pbus);
end
end
#5;
SH_LDn = 1;
K_3 = 1;
#5;
// Test shifting in bits. Not used in APPLE II.
for (i=0; i<16; i=i+1) begin
if ( i[1:0]==0 ) begin
J_2 = 0; K_3 = 1;
end else begin
J_2 = 1; K_3 = 0;
end
CP_10 = 0;
#5
CP_10 = 1;
#5;
end
#10;
if (errct == 0) begin
$display("PASSED");
end else begin
$display("FAILED errct=%d", errct);
end
$finish;
end
endmodule

7
AppleIIGateSch/chipi74LS153.cmd_log Normal file
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sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch
sch2sym -intstyle ise -family spartan3e -refsym chipi74LS153 C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sym
sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch
sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch
sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch
sch2hdl -intstyle ise -family spartan3e -verilog chipi74LS153_drc.vf -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch
sch2verilog -intstyle ise -family spartan3e -tionly {} -tiext tfi -w C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chipi74LS153.sch chipi74LS153.tfi

1
AppleIIGateSch/chipi74LS153.jhd Normal file
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@ -0,0 +1 @@
MODULE chipi74LS153

384
AppleIIGateSch/chipi74LS153.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
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<trait delete="all:0" />
<trait editname="all:0" />
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</attr>
<netlist>
<signal name="XLXN_1" />
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<signal name="XLXN_7" />
<signal name="XLXN_8" />
<signal name="XLXN_9" />
<signal name="Zb_9" />
<signal name="Ebn_15" />
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<text style="fontsize:52;fontname:Arial" x="2712" y="72">74LS153 from TI TTL Data Book</text>
<text style="fontsize:52;fontname:Arial" x="2788" y="156">Made for APPLE II schematic</text>
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53
AppleIIGateSch/chipi74LS153.sym Normal file
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9
AppleIIGateSch/fuse.xmsgs Normal file
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1
AppleIIGateSch/fuseRelaunch.cmd Normal file
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133
AppleIIGateSch/iseconfig/AppleIIGateSch.projectmgr Normal file
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<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
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<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
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<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
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<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
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<toc-item title="Router Information" target="Starting Router" />
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<toc-item title="Clock Report" target="Generating Clock Report" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ClockVideoGenerator_pad.txt" label="Pad Report" >
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<toc-item title="Component" target="Component " />
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<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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AppleIIGateSch/isim.log Normal file
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ISim log file
Running: C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS257_chip74LS257_sch_tb_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_chip74LS257_sch_tb_isim_beh.wdb
ISim P.20131013 (signature 0x7708f090)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 30000 ns
Simulator is doing circuit initialization process.
auto_init not defined
Finished circuit initialization process.
PASSED
Stopped at time : 10340 ns : File "C:/Users/Fred6502/Xilinx/tutorial/AppleIIGateSch/chip74LS257_tb.v" Line 102