105 lines
1.7 KiB
Verilog
105 lines
1.7 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\ClockVideoGenerator.sch - Sun Jun 03 21:54:27 2018
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`timescale 1ns / 1ps
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module ClockVideoGenerator_ClockVideoGenerator_sch_tb();
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// Inputs
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reg SOFT5_A2_11;
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reg SOFT5_A2_8;
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reg CLK_14o3M;
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// Output
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wire VA;
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wire V5;
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wire V4;
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wire V3;
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wire V2;
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wire V1;
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wire V0;
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wire VC;
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wire VB;
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wire H5;
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wire H4;
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wire H3;
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wire H2;
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wire H1;
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wire H0;
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wire RASn;
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wire CASn;
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wire AX;
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wire Q3;
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wire LDPSn;
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wire LD194;
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wire PHI0;
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wire PHI1;
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wire COLOR_REF;
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wire c7M;
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wire c7Mn;
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// Bidirs
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// TB vars and stuff
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integer i;
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// Instantiate the UUT
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ClockVideoGenerator UUT (
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.SOFT5_A2_11(SOFT5_A2_11),
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.V5(V5),
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.V4(V4),
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.V3(V3),
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.V2(V2),
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.V1(V1),
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.V0(V0),
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.VC(VC),
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.VB(VB),
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.VA(VA),
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.H5(H5),
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.H4(H4),
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.H3(H3),
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.H2(H2),
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.H1(H1),
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.H0(H0),
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.SOFT5_A2_8(SOFT5_A2_8),
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.RASn(RASn),
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.CASn(CASn),
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.AX(AX),
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.Q3(Q3),
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.LDPSn(LDPSn),
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.LD194(LD194),
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.PHI0(PHI0),
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.PHI1(PHI1),
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.COLOR_REF(COLOR_REF),
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.c7M(c7M),
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.c7Mn(c7Mn),
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.CLK_14o3M(CLK_14o3M)
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);
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// Initialize Inputs
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`ifdef auto_init
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initial begin
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$display("auto_init set");
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end
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`else
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initial begin
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$display("NOT SET auto_init");
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end
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`endif
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initial begin
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SOFT5_A2_11 = 0;
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SOFT5_A2_8 = 0;
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#5
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SOFT5_A2_11 = 1;
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SOFT5_A2_8 = 1;
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#5
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CLK_14o3M = 0;
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#100
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for (i=0; i<3000; i = i + 1) begin
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CLK_14o3M = 0;
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#5;
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CLK_14o3M = 1;
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#5;
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end
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$finish;
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end
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endmodule
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