mirror of
https://github.com/fred6502/Apple-II-Gate-Level-Xilinx-ISE-14.7-Schematic-Entry.git
synced 2024-12-04 12:49:25 +00:00
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iseconfig | ||
AppleIIGateSch.gise | ||
AppleIIGateSch.xise | ||
chip74LS153_tb.v | ||
chip74LS161_guide.ncd | ||
chip74LS161_tb.v | ||
chip74LS161.jhd | ||
chip74LS161.sch | ||
chip74LS161.schbak | ||
chip74LS161.schcmd | ||
chip74LS161.sym | ||
chip74LS175_beh.prj | ||
chip74LS175_tb.v | ||
chip74LS175.cmd_log | ||
chip74LS175.jhd | ||
chip74LS175.sch | ||
chip74LS175.sym | ||
chip74LS257_tb.v | ||
chip74LS257.jhd | ||
chip74LS257.sch | ||
chip74LS257.sym | ||
chip74S195_tb.v | ||
chip74S195.cmd_log | ||
chip74S195.jhd | ||
chip74S195.sch | ||
chip74S195.sym | ||
chipi74LS153.cmd_log | ||
chipi74LS153.jhd | ||
chipi74LS153.sch | ||
chipi74LS153.sym | ||
ClockVideoGenerator_guide.ncd | ||
ClockVideoGenerator_isim_beh1.wdb | ||
ClockVideoGenerator_summary.html | ||
ClockVideoGenerator_tb.v | ||
ClockVideoGenerator.sch | ||
ClockVideoGenerator.sym | ||
fuse.xmsgs | ||
fuseRelaunch.cmd | ||
isim.log | ||
JK_FlipFlop_JK_FlipFlop_sch_tb_beh.prj | ||
JK_FlipFlop_tb.v | ||
JK_FlipFlop.jhd | ||
JK_FlipFlop.sch | ||
JK_FlipFlop.schlog | ||
JK_FlipFlop.sym | ||
README.txt |
I, Frederick Kilner, being of sound mind and body and making a gate level Apple ][ in a FPGA. Creating a functional gate level Apple II from Apple II schematic. Using Xilinx 14.7 Schematic Entry. Making small test benches of module. Design will be loaded in to Nexsys-2 Spartan3E-500 board. Also manually entering 74series chips(gate level schemtic). I didn't find a 74series library so have to enter my own chips. My goal is to have a functional gate level apple II in an FPGA. I want to be able to connect it to the composite input of a monitor. I'll need a few analog components for that. Also I will want to have a module which reads the generated composite signal and drives the analog VGA port. That will probably require a frame buffer unless 59.94Hz refresh rate is okay for some VGA mode. Voltage level shifters will be needed but I have expansion connections and want to be able to plug in real Apple II cards including disk drive card and music card and 80 column card. I want to be able to prototype Apple II hardware changes in FPGA board. Verilog generated from Xilinx ISE can be used in Xilinx Vivado project to have apple II on Artix-7 chip. Verilog can be used in other design tool for other chips/boards.. such as Quartus-II or whatever it is now. FPGA is neat.