62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\JK_FlipFlop.sch - Mon May 21 17:10:31 2018
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// On positive clock EDGE
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// J=0 K=0 outputs Q,Qnot unchanged
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// J=1 K=1 outputs Q,Qnot toggled.
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// J=1 K=0 outputs Q=1, Qnot=0
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// J=0 K=1 outputs Q=0, Qnot=1
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`timescale 1ns / 1ps
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module JK_FlipFlop_JK_FlipFlop_sch_tb();
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// Inputs
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reg CLK;
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reg J;
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reg K;
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// Output
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wire Q;
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wire Qnot;
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integer i;
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// Bidirs
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// Instantiate the UUT
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JK_FlipFlop UUT (
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.Q(Q),
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.Qnot(Qnot),
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.CLK(CLK),
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.J(J),
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.K(K)
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);
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// Initialize Inputs
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// `ifdef auto_init
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// initial begin
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// CLK = 0;
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// J = 0;
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// K = 0;
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// `endif
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initial begin
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J=0; K=0; CLK=0;
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#2 force UUT.Q_DUMMY = 0; force UUT.Qnot_DUMMY = 1;
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#2 CLK=1;
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#2 CLK=0;
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#2 release UUT.Q_DUMMY;
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#2 release UUT.Qnot_DUMMY;
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#4;
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J = 0;
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K = 0;
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CLK = 0; #4;
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CLK = 1; #4;
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for (i=0; i<320; i=i+1) begin
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CLK = i & 1;
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J = (i >> 1) & 1;
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K = (i >> 2) & 1;
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$display("CLK=%b J=%b K=%b Q=%b Qnot=%b clock=%d", CLK, J, K, Q, Qnot, $time);
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#2;
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end
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// $finish;
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end
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endmodule
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