109 lines
2.2 KiB
Verilog
109 lines
2.2 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chipi74LS153.sch - Sun May 27 17:02:08 2018
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`timescale 1ns / 1ps
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module chipi74LS153_chipi74LS153_sch_tb();
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// Inputs
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reg Ebn_15;
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reg b0_10;
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reg b1_11;
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reg b2_12;
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reg b3_13;
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reg Ean_11;
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reg a0_6;
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reg a1_5;
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reg a2_4;
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reg a3_3;
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reg S0_14;
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reg S1_2;
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// Output
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wire Zb_9;
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wire Za_7;
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// Simulate test bench vars
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integer i, j, errct;
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wire [3:0] abus;
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wire [3:0] bbus;
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assign abus = { a3_3, a2_4, a1_5, a0_6 };
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assign bbus = { b3_13, b2_12, b1_11, b0_10 };
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reg expectedA, expectedB; // Just for simulation
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// Bidirs
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// Instantiate the UUT
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chipi74LS153 UUT (
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.Zb_9(Zb_9),
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.Ebn_15(Ebn_15),
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.b0_10(b0_10),
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.b1_11(b1_11),
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.b2_12(b2_12),
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.b3_13(b3_13),
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.Za_7(Za_7),
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.Ean_11(Ean_11),
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.a0_6(a0_6),
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.a1_5(a1_5),
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.a2_4(a2_4),
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.a3_3(a3_3),
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.S0_14(S0_14),
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.S1_2(S1_2)
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);
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// Initialize Inputs
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`ifdef auto_init
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initial begin
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$display("auto_init is defined");
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end
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`else
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initial begin
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$display("not defined auto_init");
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end
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`endif
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initial begin
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Ebn_15 = 0;
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b0_10 = 0;
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b1_11 = 0;
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b2_12 = 0;
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b3_13 = 0;
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Ean_11 = 0;
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a0_6 = 0;
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a1_5 = 0;
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a2_4 = 0;
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a3_3 = 0;
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S0_14 = 0;
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S1_2 = 0;
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errct = 0;
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#5;
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for (i=0; i<256; i=i+1) begin
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a0_6 = i[0];
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a1_5 = i[1];
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a2_4 = i[2];
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a3_3 = i[3];
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b0_10 = i[4];
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b1_11 = i[5];
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b2_12 = i[6];
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b3_13 = i[7];
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#10;
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for (j=0; j<16; j=j+1) begin
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Ean_11 = j[0];
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Ebn_15 = j[1];
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S0_14 = j[2];
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S1_2 = j[3];
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#5;
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expectedA = (~Ean_11) & abus[{S1_2,S0_14}];
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expectedB = (~Ebn_15) & bbus[{S1_2,S0_14}];
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if (expectedA != Za_7) begin
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$display("ERR: expectedA=%b Za=%b a=%b S1=%b S0=%b Ean=%b",
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expectedA, Za_7, abus, bbus, S1_2, S0_14, Ean_11);
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errct = errct + 1;
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end
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end
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end
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if ( errct == 0 ) begin
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$display("PASSED");
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end else begin
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$display("FAILED errct=%d", errct);
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end
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end
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endmodule
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