105 lines
1.5 KiB
Verilog
105 lines
1.5 KiB
Verilog
// Verilog test fixture created from schematic C:\Users\Fred6502\Xilinx\tutorial\AppleIIGateSch\chip74LS161.sch - Wed May 23 13:17:20 2018
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`timescale 1ns / 1ps
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module chip74LS161_chip74LS161_sch_tb();
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// Inputs
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reg CLK;
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reg CLRn;
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reg PEn;
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reg CEP;
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reg CET;
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reg P0;
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reg P1;
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reg P2;
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reg P3;
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// Output
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wire Q1;
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wire Q2;
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wire Q3;
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wire TC;
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wire Q0;
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// testbench Vars
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integer i;
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// Bidirs
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// Instantiate the UUT
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chip74LS161 UUT (
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.CLK(CLK),
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.CLRn(CLRn),
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.Q0(Q0),
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.Q1(Q1),
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.Q2(Q2),
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.Q3(Q3),
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.TC(TC),
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.PEn(PEn),
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.CEP(CEP),
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.CET(CET),
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.P0(P0),
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.P1(P1),
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.P2(P2),
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.P3(P3)
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);
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// Initialize Inputs
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//`ifdef auto_init
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initial begin
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CLK = 0;
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CLRn = 0;
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PEn = 0;
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CEP = 0;
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CET = 0;
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P0 = 0;
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P1 = 0;
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P2 = 0;
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P3 = 0;
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//`endif
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#100;
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#2 CLRn = 1; #2 CLRn=0; #2 CLRn=1;
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#2; CLK=1; #1;
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CEP=1;
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CET=1;
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PEn = 1;
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for (i=0; i<40; i=i+1) begin
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CLK=0; #2;
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CLK=1; #2;
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end
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#4;
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CLK=0; #2;
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CLK=1; #2;
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P0 = 1;
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P1 = 1;
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P2 = 1;
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P3 = 1;
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PEn = 1;
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CLK=0; #2;
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CLK=1; #2;
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PEn = 0;
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CLK=0; #2;
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CLK=1; #2;
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PEn = 1;
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for (i=0; i<8; i=i+1) begin
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CLK=0; #2;
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CLK=1; #2;
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end
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#4;
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P0 = 0;
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P1 = 1;
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P2 = 1;
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P3 = 0;
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PEn = 0;
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CLK=0; #2;
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CLK=1; #2;
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PEn = 1;
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for (i=0; i<8; i=i+1) begin
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CLK=0; #2;
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CLK=1; #2;
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end
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end
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endmodule
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