Apple-II-Gate-Level-Xilinx-.../AppleIIGateSch/chip74LS175_beh.prj

mirror of https://github.com/fred6502/Apple-II-Gate-Level-Xilinx-ISE-14.7-Schematic-Entry.git
verilog work "chip74LS175.vf"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
	`verilog work "chip74LS175.vf"`
	`verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"`